diff --git a/src/main/scala/mac/MAC.scala b/src/main/scala/mac/MAC.scala
index 9af1111..78001ec 100644
--- a/src/main/scala/mac/MAC.scala
+++ b/src/main/scala/mac/MAC.scala
@@ -14,7 +14,7 @@ class Mac(implicit p: Parameters) extends LazyModule with HasMacParameters{
   val tlMasterNode =   
         TLManagerNode(Seq(TLSlavePortParameters.v1(
           managers = Seq(TLSlaveParameters.v1(
-          address = Seq(AddressSet(0x00000000L, 0x0FFFL)),
+          address = Seq(AddressSet(0x30000000L, 0x0FFFL)),
           regionType = RegionType.UNCACHED,
           executable = false,
           supportsGet         = TransferSizes(32/8, 32/8),
diff --git a/src/main/scala/mac/Rocket/RocketMac.scala b/src/main/scala/mac/Rocket/RocketMac.scala
new file mode 100644
index 0000000..2795b3c
--- /dev/null
+++ b/src/main/scala/mac/Rocket/RocketMac.scala
@@ -0,0 +1,35 @@
+// package Top
+
+// import chisel3._
+// import Mac._
+
+
+// import freechips.rocketchip.system._
+// import org.chipsalliance.cde.config.Parameters
+// import freechips.rocketchip.subsystem._
+// import freechips.rocketchip.devices.tilelink._
+// import freechips.rocketchip.util.DontTouch
+
+
+
+// /** Example Top with periphery devices and ports, and a Rocket subsystem */
+// class ExampleRocketSystem(implicit p: Parameters) extends RocketSubsystem
+//     with HasAsyncExtInterrupts
+//     with CanHaveMasterAXI4MemPort
+//     with CanHaveMasterAXI4MMIOPort
+//     with CanHaveSlaveAXI4Port
+//     with WithManyMacMix
+// {
+//   // optionally add ROM devices
+//   // Note that setting BootROMLocated will override the reset_vector for all tiles
+//   val bootROM  = p(BootROMLocated(location)).map { BootROM.attach(_, this, CBUS) }
+//   val maskROMs = p(MaskROMLocated(location)).map { MaskROM.attach(_, this, CBUS) }
+
+//   override lazy val module = new ExampleRocketSystemModuleImp(this)
+// }
+
+// class ExampleRocketSystemModuleImp[+L <: ExampleRocketSystem](_outer: L) extends RocketSubsystemModuleImp(_outer)
+//     with HasRTCModuleImp
+//     with HasExtInterruptsModuleImp
+//     with DontTouch
+
diff --git a/src/main/scala/mac/WithMac.scala b/src/main/scala/mac/WithMac.scala
index bd117df..ff9f081 100644
--- a/src/main/scala/mac/WithMac.scala
+++ b/src/main/scala/mac/WithMac.scala
@@ -12,7 +12,7 @@ trait WithManyMacMix { this: BaseSubsystem =>
     val mac = LazyModule(new Mac)
 
     fbus.coupleFrom("mac_mst") { _ := TLBuffer() := mac.tlClientNode }
-    pbus.coupleTo("mac_cfg") { mac.tlMasterNode := TLFragmenter(4, pbus.blockBytes) := TLWidthWidget(pbus.beatBytes) := _ }
+    pbus.coupleTo("mac_cfg")   { mac.tlMasterNode := _ } //TLFragmenter(4, pbus.blockBytes) := TLWidthWidget(pbus.beatBytes) := 
 
     ibus.fromSync := mac.int_node
 
diff --git a/src/test/scala/gcd/MacAXI.scala b/src/test/scala/gcd/MacAXI.scala
new file mode 100644
index 0000000..f14c272
--- /dev/null
+++ b/src/test/scala/gcd/MacAXI.scala
@@ -0,0 +1,85 @@
+package MAC
+
+import chisel3._
+import chisel3.util._
+
+import org.chipsalliance.cde.config._
+import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.tilelink._
+import freechips.rocketchip.interrupts._
+import freechips.rocketchip.amba.axi4._
+import freechips.rocketchip.devices.tilelink._
+
+class MacAXI(implicit p: Parameters) extends Mac{
+
+
+
+  val memAXI4SlaveNode = AXI4SlaveNode(Seq(
+    AXI4SlavePortParameters(
+      slaves = Seq(
+        AXI4SlaveParameters(
+          address = Seq(AddressSet(0x00000000L, 0x7fffffffL)),
+          regionType = RegionType.UNCACHED,
+          executable = true,
+          supportsRead  = TransferSizes(32/8, 32/8),
+          supportsWrite = TransferSizes(32/8, 32/8)
+        )
+      ),
+      beatBytes = 32 / 8
+    )
+  ))
+
+    memAXI4SlaveNode := 
+    AXI4UserYanker() := 
+    AXI4IdIndexer(1) :=
+    AXI4Deinterleaver(32/8) :=
+    TLToAXI4() := 
+    TLWidthWidget(32 / 8) :=
+    tlClientNode
+
+
+
+
+    val axiConfigPort = 
+      AXI4MasterNode(
+        Seq(AXI4MasterPortParameters(
+          Seq(AXI4MasterParameters(
+            name = "Mac Config",
+            id = IdRange(0, 1),
+            maxFlight = Some(1),
+          ))
+        ))
+      )
+
+    val tlError = LazyModule(new TLError(
+    params = DevNullParams(
+      address = Seq(AddressSet(0x0, 0x2fffffffL)),
+      maxAtomic = 0,
+      maxTransfer = 32/8),
+    beatBytes = 32 / 8
+  ))
+
+  val xbar = TLXbar()
+
+
+	tlMasterNode := xbar := TLFIFOFixer() := TLWidthWidget(32/8) := AXI4ToTL() := AXI4UserYanker(Some(1)) := AXI4Fragmenter() := AXI4Buffer() := AXI4IdIndexer(1) := axiConfigPort
+  tlError.node := xbar
+
+	val intSinkNode = IntSinkNode(IntSinkPortSimple())
+	intSinkNode := int_node
+
+  val axiCfg = InModuleBody {
+    axiConfigPort.makeIOs()
+  }
+
+  val axiMem = InModuleBody {
+    memAXI4SlaveNode.makeIOs()
+  }
+
+	val int = InModuleBody {
+	  intSinkNode.makeIOs()
+	}
+
+
+
+}
\ No newline at end of file
diff --git a/src/test/scala/gcd/test.scala b/src/test/scala/gcd/test.scala
index f6ee24c..9f86c7c 100644
--- a/src/test/scala/gcd/test.scala
+++ b/src/test/scala/gcd/test.scala
@@ -19,7 +19,7 @@ object testModule extends App {
 
   (new chisel3.stage.ChiselStage).execute( Array("--show-registrations", "--full-stacktrace", "--target-dir", "generated/Main") ++ args, Seq(
       ChiselGeneratorAnnotation(() => {
-    val soc = LazyModule(new MacTest()(cfg))
+    val soc = LazyModule(new MacAXI()(cfg))
     soc.module
   })
   ))