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完成编译，准备接入CPU查看信号逻辑

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This commit is contained in:
RuigeLee
2023-10-17 16:38:18 +08:00
parent 7c71c005f8
commit 629d9486d1
8 changed files with 118 additions and 191 deletions
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97
src/main/scala/Switch/RevBuff.scala
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@@ -1,97 +0,0 @@
package MAC
import chisel3._
import chisel3.util._
class RevBuff_Enq_Ctrl_Bundle extends Bundle{
val LatchedRxLength = UInt(16.W)
val RxStatusInLatched = UInt(9.W)
val isRxAbort = Bool()
}
class RevBuff_Deq_Ctrl_Bundle extends Bundle{
}
class RevBuff_Enq_Bundle extends Bundle{
val data = Decoupled(UInt(32.W))
val ctrl = Decoupled(new RevBuff_Enq_Ctrl_Bundle)
}
class RevBuff_Deq_Bundle extends Bundle{
val data = Decoupled(UInt(32.W))
val ctrl = Decoupled(new RevBuff_Deq_Ctrl_Bundle)
}
class RevBuffIO extends Bundle{
val enq = Flipped(new RevBuff_Enq_Bundle)
val deq = new RevBuff_Deq_Bundle
}
class Packet_Info_Bundle extends Bundle{
val LatchedRxLength = UInt(16.W)
val RxStatusInLatched = UInt(9.W)
val header = Vec( 5, UInt(32.W) )
}
class RevBuff extends Module{
val io: RevBuffIO = IO(new RevBuffIO)
val isPing = RegInit(true.B)
val isPong = ~isPing
val pipoBuff = for( i <- 0 until 2 ) yiled { Module(new Queue( UInt(32.W), 2048/4 )) }
val pipoInfo = for( i <- 0 until 2 ) yiled { Reg(new Packet_Info_Bundle) }
val recCnt = RegInit(0.U(3.W))
pipoBuff(0).io.enq.valid := isPing & io.enq.data.valid
pipoBuff(0).io.enq.bits := io.enq.data.bits
pipoBuff(1).io.enq.valid := isPong & io.enq.data.valid
pipoBuff(1).io.enq.btis := io.enq.data.bits
io.enq.data.ready := (isPing & io.enq.data.ready) | (isPong & io.enq.data.ready)
io.enq.ctrl.ready := true.B
pipoBuff(0).reset := reset.asBool | (isPing & io.enq.ctrl.fire & io.enq.ctrl.bits.isRxAbort)
pipoBuff(1).reset := reset.asBool | (isPong & io.enq.ctrl.fire & io.enq.ctrl.bits.isRxAbort)
when( io.enq.ctrl.fire & ~io.enq.ctrl.bits.isRxAbort){
isPing := ~isPing
when( isPing ){
pipoInfo(0).LatchedRxLength := io.enq.ctrl.bits.LatchedRxLength
pipoInfo(0).RxStatusInLatched := io.enq.ctrl.bits.RxStatusInLatched
} .elsewhen( isPong ){
pipoInfo(1).LatchedRxLength := io.enq.ctrl.bits.LatchedRxLength
pipoInfo(1).RxStatusInLatched := io.enq.ctrl.bits.RxStatusInLatched
}
}
when( io.enq.ctrl.fire ){
recCnt := 0.U
} .elsewhen( io.enq.data.fire ){
when( recCnt < 5 ){
recCnt := recCnt + 1.U
when( isPing ){
pipoInfo(0).header(recCnt) := io.enq.data.bits
} .elsewhen( isPong ){
pipoInfo(1).header(recCnt) := io.enq.data.bits
} .otherwise{
assert(false.B, "Assert Failed, Rx Under Run")
}
}
}
}

46
src/main/scala/Switch/TxBuff.scala
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@@ -1,46 +0,0 @@
package MAC
import chisel3._
import chisel3.util._
class Transmit_Enq_Ctrl_Bundle extends Bundle{
}
class Transmit_Deq_Req_Bundle extends Bundle{
}
class Transmit_Deq_Resp_Bundle extends Bundle{
}
class Transmit_Enq_Bundle extends Bundle{
val data = Decoupled(UInt(32.W))
val ctrl = Decoupled(new Transmit_Enq_Ctrl_Bundle)
}
class Transmit_Deq_Bundle extends Bundle{
val data = Decoupled(UInt(32.W))
val req = Decoupled(new Transmit_Deq_Req_Bundle)
val resp = Flipped(Decoupled(new Transmit_Deq_Resp_Bundle))
}
class TxBuffIO extends Bundle{
val enq = Flipped(new Transmit_Enq_Bundle)
val deq = new Transmit_Deq_Bundle
}
class TxBuff extends Module{
val io: TxBuffIO = IO(new TxBuffIO)
}