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修复同步操作数

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This commit is contained in:
Ruige Lee
2025-05-26 10:40:41 +08:00
parent 694cb7c9f7
commit 5fa5a4c244
2 changed files with 4 additions and 4 deletions
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4
src/main/scala/backBoard/shin/SlaveParser.scala
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@@ -624,8 +624,8 @@ trait SlaveParserSync{ this: SlaveParserBase =>
//下行接收 //下行接收
val isSync = (downRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & ( //req fire 后 已经反相 val isSync = (downRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & ( //req fire 后 已经反相
( ~isDownRecPing & downSubMsgInfo(0).devIndex === 0.U & downSubMsgInfo(0).operator === "he".U ) | ( ~isDownRecPing & downSubMsgInfo(0).devIndex === 0.U & downSubMsgInfo(0).operator === SUBMSG_OPERATOR_SYNC ) |
( isDownRecPing & downSubMsgInfo(1).devIndex === 0.U & downSubMsgInfo(1).operator === "he".U ) ( isDownRecPing & downSubMsgInfo(1).devIndex === 0.U & downSubMsgInfo(1).operator === SUBMSG_OPERATOR_SYNC )
) )
val syncCnt = Reg(UInt(4.W)) val syncCnt = Reg(UInt(4.W))

4
src/main/scala/backBoard/shin/SpiInterface.scala
View File

@@ -51,8 +51,8 @@ abstract class SpiInterfaceBase extends Module{
val addrw = Reg(UInt(16.W)) val addrw = RegInit(0.U(16.W))
val addrr = Reg(UInt(16.W)) val addrr = RegInit(0.U(16.W))
val spiCmd = Reg(UInt(8.W)) val spiCmd = Reg(UInt(8.W))
val isSpiWrite = spiCmd === 0.U val isSpiWrite = spiCmd === 0.U