From 5fa5a4c2445be9732de42799326fb04f18f270b1 Mon Sep 17 00:00:00 2001 From: Ruige Lee Date: Mon, 26 May 2025 10:40:41 +0800 Subject: [PATCH] =?UTF-8?q?=E4=BF=AE=E5=A4=8D=E5=90=8C=E6=AD=A5=E6=93=8D?= =?UTF-8?q?=E4=BD=9C=E6=95=B0?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/shin/SlaveParser.scala | 4 ++-- src/main/scala/backBoard/shin/SpiInterface.scala | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/main/scala/backBoard/shin/SlaveParser.scala b/src/main/scala/backBoard/shin/SlaveParser.scala index 9d456c0..530a73c 100644 --- a/src/main/scala/backBoard/shin/SlaveParser.scala +++ b/src/main/scala/backBoard/shin/SlaveParser.scala @@ -624,8 +624,8 @@ trait SlaveParserSync{ this: SlaveParserBase => //下行接收 val isSync = (downRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & ( //req fire 后 已经反相 - ( ~isDownRecPing & downSubMsgInfo(0).devIndex === 0.U & downSubMsgInfo(0).operator === "he".U ) | - ( isDownRecPing & downSubMsgInfo(1).devIndex === 0.U & downSubMsgInfo(1).operator === "he".U ) + ( ~isDownRecPing & downSubMsgInfo(0).devIndex === 0.U & downSubMsgInfo(0).operator === SUBMSG_OPERATOR_SYNC ) | + ( isDownRecPing & downSubMsgInfo(1).devIndex === 0.U & downSubMsgInfo(1).operator === SUBMSG_OPERATOR_SYNC ) ) val syncCnt = Reg(UInt(4.W)) diff --git a/src/main/scala/backBoard/shin/SpiInterface.scala b/src/main/scala/backBoard/shin/SpiInterface.scala index 8a9c339..8bc4c1e 100644 --- a/src/main/scala/backBoard/shin/SpiInterface.scala +++ b/src/main/scala/backBoard/shin/SpiInterface.scala @@ -51,8 +51,8 @@ abstract class SpiInterfaceBase extends Module{ - val addrw = Reg(UInt(16.W)) - val addrr = Reg(UInt(16.W)) + val addrw = RegInit(0.U(16.W)) + val addrr = RegInit(0.U(16.W)) val spiCmd = Reg(UInt(8.W)) val isSpiWrite = spiCmd === 0.U