修复同步操作数

2025-05-26 10:40:41 +08:00
parent 694cb7c9f7
commit 5fa5a4c244
2 changed files with 4 additions and 4 deletions
--- a/src/main/scala/backBoard/shin/SpiInterface.scala
+++ b/src/main/scala/backBoard/shin/SpiInterface.scala
@@ -51,8 +51,8 @@ abstract class SpiInterfaceBase extends Module{



-  val addrw = Reg(UInt(16.W))
-  val addrr = Reg(UInt(16.W))
+  val addrw = RegInit(0.U(16.W))
+  val addrr = RegInit(0.U(16.W))
  val spiCmd  = Reg(UInt(8.W))

  val isSpiWrite = spiCmd === 0.U