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带布局布线策略可以通过时序

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This commit is contained in:
RuigeLee
2024-10-23 11:41:24 +08:00
parent 77a43b438b
commit 5d5fce6747
1 changed files with 24 additions and 4 deletions
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28
src/main/scala/backBoard/shin/ShinSlv.scala
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@@ -283,7 +283,26 @@ trait ShinSlvPhyUpStreamRecv{ this: ShinSlvPhyDownStream =>
//---------------
when( (upRecvStateCurr === UpRecvStateOHead & upPendBuf.io.deq.fire) ){
upOldHead := Cat( upOldHead.asUInt.tail(8), upPendBuf.io.deq.bits.tdata ).asTypeOf(new Header_Info_Bundle)
// upOldHead := Cat( upOldHead.asUInt.tail(8), upPendBuf.io.deq.bits.tdata ).asTypeOf(new Header_Info_Bundle)
when( upRecvCnt === 1.U ) {
upOldHead.length := upPendBuf.io.deq.bits.tdata
} .elsewhen( upRecvCnt === 2.U ) {
upOldHead.length := Cat( upOldHead.length, upPendBuf.io.deq.bits.tdata(7,4) )
upOldHead.operator := upPendBuf.io.deq.bits.tdata(3,0)
} .elsewhen( upRecvCnt === 3.U ){
upOldHead.param(0) := upPendBuf.io.deq.bits.tdata
} .elsewhen( upRecvCnt === 4.U ){
upOldHead.param(0) := Cat( upOldHead.param(0), upPendBuf.io.deq.bits.tdata )
} .elsewhen( upRecvCnt === 5.U ){
upOldHead.param(1) := upPendBuf.io.deq.bits.tdata
} .elsewhen( upRecvCnt === 6.U ){
upOldHead.param(1) := Cat( upOldHead.param(1), upPendBuf.io.deq.bits.tdata )
} .elsewhen( upRecvCnt === 7.U ){
upOldHead.param(2) := upPendBuf.io.deq.bits.tdata
} .elsewhen( upRecvCnt === 8.U ){
upOldHead.param(2) := Cat( upOldHead.param(2), upPendBuf.io.deq.bits.tdata )
}
} .elsewhen( isLastDownStreamEnd ){
upOldHead.operator := downOldHead.operator
upOldHead.length := 0.U
@@ -330,7 +349,7 @@ trait ShinSlvPhyUpStreamRecv{ this: ShinSlvPhyDownStream =>
upPendBuf.io.deq.ready :=
(upRecvStateCurr === UpRecvStateOHead) |
((upRecvStateCurr === UpRecvStateFData) & upForwardFifo.io.enq.ready) |
(upRecvStateCurr === UpRecvStateFData) |
(upRecvStateCurr === UpRecvStateCRC )
@@ -431,6 +450,7 @@ trait ShinSlvPhyUpStreamSend{ this: ShinSlvPhyDownStream =>
upSendStateCurr === UpSendStateFData & upStreamCdrOut.io.axis.ready
assert( ~(upStreamCdrIn.io.axis.valid & ~upStreamCdrIn.io.axis.ready) )
assert( ~(upSendStateCurr === UpSendStateFData & ~upForwardFifo.io.deq.valid) )
val isUpStreamEnd = (upSendStateCurr =/= UpSendStateIdle) & (upSendStateNext === UpSendStateIdle)
@@ -495,8 +515,8 @@ trait ShinSlvLinkInit{ this: ShinSlvLinkBase =>
isDownUpdate := false.B
}
when( (isDownNewHeadCreated | isLastDownStreamEnd) & isLegalInitDownHead ){
slvRTC := (64.U - (downOldHead.length >> 3)) << 5 // * 32
when( isUpStreamEnd ){
slvRTC := upOldHead.length >> 3 //Need Calibration
} .otherwise{
slvRTC := slvRTC + 1.U
}