diff --git a/src/main/scala/backBoard/shin/ShinSlv.scala b/src/main/scala/backBoard/shin/ShinSlv.scala
index 53266d5..96c4f50 100644
--- a/src/main/scala/backBoard/shin/ShinSlv.scala
+++ b/src/main/scala/backBoard/shin/ShinSlv.scala
@@ -283,7 +283,26 @@ trait ShinSlvPhyUpStreamRecv{ this: ShinSlvPhyDownStream =>
   //---------------
 
   when( (upRecvStateCurr === UpRecvStateOHead & upPendBuf.io.deq.fire) ){
-    upOldHead := Cat( upOldHead.asUInt.tail(8), upPendBuf.io.deq.bits.tdata ).asTypeOf(new Header_Info_Bundle)
+    // upOldHead := Cat( upOldHead.asUInt.tail(8), upPendBuf.io.deq.bits.tdata ).asTypeOf(new Header_Info_Bundle)
+
+    when( upRecvCnt === 1.U ) {
+      upOldHead.length := upPendBuf.io.deq.bits.tdata
+    } .elsewhen( upRecvCnt === 2.U ) {
+      upOldHead.length   := Cat( upOldHead.length, upPendBuf.io.deq.bits.tdata(7,4) )
+      upOldHead.operator := upPendBuf.io.deq.bits.tdata(3,0)
+    } .elsewhen( upRecvCnt === 3.U ){
+      upOldHead.param(0) := upPendBuf.io.deq.bits.tdata
+    } .elsewhen( upRecvCnt === 4.U ){
+      upOldHead.param(0) := Cat( upOldHead.param(0), upPendBuf.io.deq.bits.tdata )
+    } .elsewhen( upRecvCnt === 5.U ){
+      upOldHead.param(1) := upPendBuf.io.deq.bits.tdata
+    } .elsewhen( upRecvCnt === 6.U ){
+      upOldHead.param(1) := Cat( upOldHead.param(1), upPendBuf.io.deq.bits.tdata )
+    } .elsewhen( upRecvCnt === 7.U ){
+      upOldHead.param(2) := upPendBuf.io.deq.bits.tdata
+    } .elsewhen( upRecvCnt === 8.U ){
+      upOldHead.param(2) := Cat( upOldHead.param(2), upPendBuf.io.deq.bits.tdata )
+    }
   } .elsewhen( isLastDownStreamEnd ){
     upOldHead.operator := downOldHead.operator
     upOldHead.length   := 0.U
@@ -330,7 +349,7 @@ trait ShinSlvPhyUpStreamRecv{ this: ShinSlvPhyDownStream =>
 
   upPendBuf.io.deq.ready := 
     (upRecvStateCurr === UpRecvStateOHead) |
-    ((upRecvStateCurr === UpRecvStateFData) & upForwardFifo.io.enq.ready) |
+    (upRecvStateCurr === UpRecvStateFData) |
     (upRecvStateCurr === UpRecvStateCRC  )
 
 
@@ -431,6 +450,7 @@ trait ShinSlvPhyUpStreamSend{ this: ShinSlvPhyDownStream =>
     upSendStateCurr === UpSendStateFData & upStreamCdrOut.io.axis.ready
 
   assert( ~(upStreamCdrIn.io.axis.valid & ~upStreamCdrIn.io.axis.ready) )
+  assert( ~(upSendStateCurr === UpSendStateFData & ~upForwardFifo.io.deq.valid) )
 
   val isUpStreamEnd = (upSendStateCurr =/= UpSendStateIdle) & (upSendStateNext === UpSendStateIdle)
 
@@ -495,8 +515,8 @@ trait ShinSlvLinkInit{ this: ShinSlvLinkBase =>
     isDownUpdate := false.B
   }
 
-  when( (isDownNewHeadCreated | isLastDownStreamEnd) & isLegalInitDownHead ){
-    slvRTC := (64.U - (downOldHead.length >> 3)) << 5 // * 32
+  when( isUpStreamEnd ){
+    slvRTC := upOldHead.length >> 3 //Need Calibration
   } .otherwise{
     slvRTC := slvRTC + 1.U
   }