fpga sync

Makefile

@@ -2,9 +2,8 @@
 .PHONY: compile
 
 compile:
-	rm -rf ./generated/Main/
+	rm -rf ./generated/
-	sbt "test:runMain test.testModule \
+	sbt "test:runMain test.testModule"
-	-e verilog"
 
 
 

src/main/scala/backBoard/LocalRegisters.scala

@@ -28,4 +28,9 @@ trait LocalRegisters { this: BackBoardSlvBase =>
   }
 
 
+  val led = IO(Output(UInt(3.W)))
+  val sw  = IO( Input(UInt(1.W)))
+
+  led := digitalOut(2,0)
+  digitalIn := sw
 }

src/test/scala/gcd/test.scala

@@ -12,10 +12,12 @@ import org.chipsalliance.cde.config._
 
 
 object testModule extends App {
-  (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-e", "verilog" ) ++ args, Seq(
+  (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-E", "verilog" ) ++ args, Seq(
-      ChiselGeneratorAnnotation(() => {
+      ChiselGeneratorAnnotation(() => { new BackBoardMst }),
-    new BackPlaneMstTest
+    ))
-  })
+
+  (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-E", "verilog" ) ++ args, Seq(
+      ChiselGeneratorAnnotation(() => { new BackBoardSlv })
     ))
 
   // val cfg = new MacCfg