diff --git a/Makefile b/Makefile
index 63039fe..28543e7 100644
--- a/Makefile
+++ b/Makefile
@@ -2,9 +2,8 @@
 .PHONY: compile
 
 compile:
-	rm -rf ./generated/Main/
-	sbt "test:runMain test.testModule \
-	-e verilog"
+	rm -rf ./generated/
+	sbt "test:runMain test.testModule"
 
 
 
diff --git a/src/main/scala/backBoard/LocalRegisters.scala b/src/main/scala/backBoard/LocalRegisters.scala
index 92767f4..c74dce5 100644
--- a/src/main/scala/backBoard/LocalRegisters.scala
+++ b/src/main/scala/backBoard/LocalRegisters.scala
@@ -28,4 +28,9 @@ trait LocalRegisters { this: BackBoardSlvBase =>
   }
 
 
+  val led = IO(Output(UInt(3.W)))
+  val sw  = IO( Input(UInt(1.W)))
+
+  led := digitalOut(2,0)
+  digitalIn := sw
 }
\ No newline at end of file
diff --git a/src/test/scala/gcd/test.scala b/src/test/scala/gcd/test.scala
index 338dad7..20245e3 100644
--- a/src/test/scala/gcd/test.scala
+++ b/src/test/scala/gcd/test.scala
@@ -12,10 +12,12 @@ import org.chipsalliance.cde.config._
 
 
 object testModule extends App {
-  (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-e", "verilog" ) ++ args, Seq(
-      ChiselGeneratorAnnotation(() => {
-    new BackPlaneMstTest
-  })
+  (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-E", "verilog" ) ++ args, Seq(
+      ChiselGeneratorAnnotation(() => { new BackBoardMst }),
+    ))
+
+  (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-E", "verilog" ) ++ args, Seq(
+      ChiselGeneratorAnnotation(() => { new BackBoardSlv })
     ))
 
   // val cfg = new MacCfg