fpga sync

2023-08-01 15:50:53 +08:00
parent 35e6fcdb52
commit 5d43600680
3 changed files with 13 additions and 7 deletions
--- a/src/test/scala/gcd/test.scala
+++ b/src/test/scala/gcd/test.scala
@@ -12,10 +12,12 @@ import org.chipsalliance.cde.config._


 object testModule extends App {
-  (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-e", "verilog" ) ++ args, Seq(
-      ChiselGeneratorAnnotation(() => {
-    new BackPlaneMstTest
-  })
+  (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-E", "verilog" ) ++ args, Seq(
+      ChiselGeneratorAnnotation(() => { new BackBoardMst }),
+    ))
+
+  (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-E", "verilog" ) ++ args, Seq(
+      ChiselGeneratorAnnotation(() => { new BackBoardSlv })
    ))

  // val cfg = new MacCfg