fpga sync

src/main/scala/backBoard/LocalRegisters.scala

@@ -28,4 +28,9 @@ trait LocalRegisters { this: BackBoardSlvBase =>
   }
 
 
+  val led = IO(Output(UInt(3.W)))
+  val sw  = IO( Input(UInt(1.W)))
+
+  led := digitalOut(2,0)
+  digitalIn := sw
 }