fpga sync

2023-08-01 15:50:53 +08:00
parent 35e6fcdb52
commit 5d43600680
3 changed files with 13 additions and 7 deletions
--- a/5
+++ b/5
@@ -2,9 +2,8 @@
 .PHONY: compile

 compile:
-	rm -rf ./generated/Main/
-	sbt "test:runMain test.testModule \
-	-e verilog"
+	rm -rf ./generated/
+	sbt "test:runMain test.testModule"