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处理同步在正负边缘的bug

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This commit is contained in:
Ruige Lee
2025-05-26 17:13:06 +08:00
parent 6ab95ae178
commit 5be78365cd
1 changed files with 2 additions and 1 deletions
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3
src/main/scala/backBoard/shin/SlaveParser.scala
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@@ -674,7 +674,8 @@ trait SlaveParserSync{ this: SlaveParserBase =>
} }
when( RegNext(isSync) & ~isSync ){ when( RegNext(isSync) & ~isSync ){
deltaMstSlvDeltaTimeStamp := (mstDeltaTimeStamp - slvDeltaTimeStamp) >> 1 val deltaMstSlvDeltaTimeStamp_org = mstDeltaTimeStamp - slvDeltaTimeStamp
deltaMstSlvDeltaTimeStamp := Cat( deltaMstSlvDeltaTimeStamp_org.extract(deltaMstSlvDeltaTimeStamp_org.getWidth-1), deltaMstSlvDeltaTimeStamp_org(deltaMstSlvDeltaTimeStamp_org.getWidth-1, 1) ) //(mstDeltaTimeStamp - slvDeltaTimeStamp) >> 1
} .elsewhen( RegNext(RegNext(isSync)) & ~RegNext(isSync) ){ } .elsewhen( RegNext(RegNext(isSync)) & ~RegNext(isSync) ){
deltaFinal := mstSlvDeltaTimeStamp + deltaMstSlvDeltaTimeStamp deltaFinal := mstSlvDeltaTimeStamp + deltaMstSlvDeltaTimeStamp
} }