From 5be78365cd9db6300a00edbd3bf2ffb177a3e82c Mon Sep 17 00:00:00 2001 From: Ruige Lee Date: Mon, 26 May 2025 17:13:06 +0800 Subject: [PATCH] =?UTF-8?q?=E5=A4=84=E7=90=86=E5=90=8C=E6=AD=A5=E5=9C=A8?= =?UTF-8?q?=E6=AD=A3=E8=B4=9F=E8=BE=B9=E7=BC=98=E7=9A=84bug?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/shin/SlaveParser.scala | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/main/scala/backBoard/shin/SlaveParser.scala b/src/main/scala/backBoard/shin/SlaveParser.scala index 987bcb7..5bab42e 100644 --- a/src/main/scala/backBoard/shin/SlaveParser.scala +++ b/src/main/scala/backBoard/shin/SlaveParser.scala @@ -674,7 +674,8 @@ trait SlaveParserSync{ this: SlaveParserBase => } when( RegNext(isSync) & ~isSync ){ - deltaMstSlvDeltaTimeStamp := (mstDeltaTimeStamp - slvDeltaTimeStamp) >> 1 + val deltaMstSlvDeltaTimeStamp_org = mstDeltaTimeStamp - slvDeltaTimeStamp + deltaMstSlvDeltaTimeStamp := Cat( deltaMstSlvDeltaTimeStamp_org.extract(deltaMstSlvDeltaTimeStamp_org.getWidth-1), deltaMstSlvDeltaTimeStamp_org(deltaMstSlvDeltaTimeStamp_org.getWidth-1, 1) ) //(mstDeltaTimeStamp - slvDeltaTimeStamp) >> 1 } .elsewhen( RegNext(RegNext(isSync)) & ~RegNext(isSync) ){ deltaFinal := mstSlvDeltaTimeStamp + deltaMstSlvDeltaTimeStamp }