compile pass

src/main/scala/backBoard/BackBoardMst.scala

@@ -5,7 +5,7 @@ import chisel3.util._
 
 class FSMC_Port_Bundle extends Bundle{
 
-  val addr    = Input(UInt(12.W))
+  val addr    = Input(UInt(13.W))
   val dataIn  = Input(UInt(8.W))
   val dataOut = Output(UInt(8.W))
   val dataOEn = Output(Bool())
@@ -38,8 +38,8 @@ class BackBoardMstBase extends RawModule{
   val mirrorDown = Module(new MirrorSRAM)
   val mirrorUp = Module(new MirrorSRAM)
 
-  val status  = Reg(UInt(8.W))
+    val status  = Wire(UInt(8.W))
-  val slvNum  = Reg(UInt(5.W))
+    val slvNum  = Wire(UInt(5.W))
 
 
   mirrorDown.io.clock := io.ides_pclk.asBool
@@ -54,6 +54,9 @@ class BackBoardMstBase extends RawModule{
 trait BackBoardMstFSMC{ this: BackBoardMstBase =>
 
   withClockAndReset( io.ides_pclk.asClock, io.reset ){
+    val statusReg = RegInit(0.U(8.W)); status := statusReg
+    val slvNumReg = RegInit(0.U(5.W)); slvNum := slvNumReg
+
     val fsmcAddrSync   = ShiftRegister( io.FSMC.addr,   2, 0.U, true.B )
     val fsmcdataInSync = ShiftRegister( io.FSMC.dataIn, 2, 0.U, true.B )
     val fsmcCEnSync    = ShiftRegister( io.FSMC.cen,    2, true.B, true.B )
@@ -82,11 +85,11 @@ trait BackBoardMstFSMC{ this: BackBoardMstBase =>
     ))
 
     when( (~fsmcCEnSync & fsmcAddrSync.extract(12) & (~fsmcWEnSync) ) & (fsmcAddrSync(10,0) === 0.U) ){
-      status := fsmcdataInSync
+      statusReg := fsmcdataInSync
     }
 
     when( (~fsmcCEnSync & fsmcAddrSync.extract(12) & (~fsmcWEnSync) ) & (fsmcAddrSync(10,0) === 1.U) ){
-      slvNum := fsmcdataInSync
+      slvNumReg := fsmcdataInSync
     }
 
   }
@@ -217,3 +220,5 @@ trait BackBoardMstLVDS{ this: BackBoardMstBase =>
 
 
 }
+
+class BackBoardMst extends BackBoardMstBase with BackBoardMstFSMC with BackBoardMstLVDS

src/main/scala/backBoard/BackBoardSlv.scala

@@ -32,12 +32,12 @@ abstract class BackBoardSlvBase extends RawModule{
   
 
   lvdsSlv.io.lvds_down_din  := io.lvds_down_din 
-  lvdsSlv.io.lvds_down_dout := io.lvds_down_dout
+  io.lvds_down_dout := lvdsSlv.io.lvds_down_dout
   lvdsSlv.io.lvds_up_din    := io.lvds_up_din   
-  lvdsSlv.io.lvds_up_dout   := io.lvds_up_dout  
+  io.lvds_up_dout   := lvdsSlv.io.lvds_up_dout
     
-  val downReg = Reg(Vec(32, UInt(8.W)))
+  val downRegWire = Wire(Vec(32, UInt(8.W)))
-  val upReg   = Reg(Vec(32, UInt(8.W)))
+  val upRegWire   = Wire(Vec(32, UInt(8.W)))
 
 
 
@@ -50,8 +50,8 @@ abstract class BackBoardSlvBase extends RawModule{
   // val downstream_rx_cdr_err = Output(Bool())
   // val downstream_sync = Output(Bool())
 
-  val upstream_tx_data_ready = Output(Bool())
+  // val upstream_tx_data_ready = Output(Bool())
-  val upstream_tx_data_in = Input(UInt(8.W))
+  // val upstream_tx_data_in = Input(UInt(8.W))
 
   // val upstream_rx_crc_valid = Output(Bool())
   // val upstream_rx_crc_err = Output(Bool())
@@ -63,9 +63,13 @@ abstract class BackBoardSlvBase extends RawModule{
 trait BackBoardSlvDown{ this: BackBoardSlvBase =>
 
   withClockAndReset( io.ides_pclk.asClock, io.reset ){
+
+    val downReg = Reg(Vec(32, UInt(8.W))); downRegWire := downReg
+
+
     val downCnt = RegInit(0.U(6.W))
     val downTimeoutEn  = RegInit( false.B )
-    val downTimeoutRst = (downCnt === 0.U & downstream_rx_data_valid)
+    val downTimeoutRst = (downCnt === 0.U & lvdsSlv.io.downstream_rx_data_valid)
     val ( _, downTimeout ) = Counter( Range( 0,1023 ), downTimeoutEn, downTimeoutRst )
 
 
@@ -74,8 +78,8 @@ trait BackBoardSlvDown{ this: BackBoardSlvBase =>
         downReg(i) := 0.U
       }
     } .otherwise{
-      when( downstream_rx_data_valid ){
+      when( lvdsSlv.io.downstream_rx_data_valid ){
-        downReg(downCnt) := downstream_rx_data_out
+        downReg(downCnt) := lvdsSlv.io.downstream_rx_data_out
       }
     }
 
@@ -83,7 +87,7 @@ trait BackBoardSlvDown{ this: BackBoardSlvBase =>
       downTimeoutEn := false.B
     } .elsewhen( downCnt === 32.U ){
       downTimeoutEn := false.B
-    } .elsewhen(downCnt === 0.U & downstream_rx_data_valid){
+    } .elsewhen(downCnt === 0.U & lvdsSlv.io.downstream_rx_data_valid){
       downTimeoutEn := true.B
     }
 
@@ -91,7 +95,7 @@ trait BackBoardSlvDown{ this: BackBoardSlvBase =>
       downCnt := 0.U
     }.elsewhen( downCnt === 32.U ){
       downCnt := 0.U
-    }.elsewhen( downstream_rx_data_valid ){
+    }.elsewhen( lvdsSlv.io.downstream_rx_data_valid ){
       downCnt := downCnt + 1.U
     }
 
@@ -103,16 +107,18 @@ trait BackBoardSlvUp{ this: BackBoardSlvBase =>
   withClockAndReset( io.ides_pclk.asClock, io.reset ){
     val upCnt = RegInit(0.U(6.W))
     val upTimeoutEn  = RegInit( false.B )
-    val upTimeoutRst = (upCnt === 0.U & upstream_tx_data_ready)
+    val upTimeoutRst = (upCnt === 0.U & lvdsSlv.io.upstream_tx_data_ready)
     val ( _, upTimeout ) = Counter( Range( 0,1023 ), upTimeoutEn, upTimeoutRst )
 
+
+    lvdsSlv.io.upstream_tx_data_in := upRegWire(upCnt)
       // when( upstream_tx_data_ready ){
-      //   upstream_tx_data_ready := upReg(upCnt)
+      //   upstream_tx_data_ready := upRegWire(upCnt)
       // }
 
     when( io.reset ){
       for( i <- 0 until 32 ){
-        upReg(i) := 0.U
+        upRegWire(i) := 0.U
       }
     } .otherwise{
 
@@ -122,18 +128,20 @@ trait BackBoardSlvUp{ this: BackBoardSlvBase =>
       upTimeoutEn := false.B
     } .elsewhen( upCnt === 32.U ){
       upTimeoutEn := false.B
-    } .elsewhen(upCnt === 0.U & upstream_tx_data_ready){
+    } .elsewhen(upCnt === 32.U & lvdsSlv.io.upstream_tx_data_ready){
       upTimeoutEn := true.B
     }
 
     when( upTimeout ){
       upCnt := 0.U
-    }.elsewhen( upCnt === 32.U ){
+    }.elsewhen( upCnt === 32.U & lvdsSlv.io.upstream_tx_data_ready ){
       upCnt := 0.U
-    }.elsewhen( upstream_tx_data_ready ){
+    }.elsewhen( lvdsSlv.io.upstream_tx_data_ready ){
       upCnt := upCnt + 1.U
     }
 
   }
 }
 
+
+

src/main/scala/backBoard/LocalRegisters.scala

@@ -4,173 +4,193 @@ import chisel3._
 import chisel3.util._
 
 
+class BackBoardSlvDigitalIO extends BackBoardSlvBase with BackBoardSlvDown with BackBoardSlvUp{
+  val in  = IO(Input(UInt(32.W)))
+  val out = IO(Output(UInt(32.W)))
+  val oe  = IO(Output(UInt(32.W)))
 
+  withClockAndReset( io.ides_pclk.asClock, io.reset ){
+    val upReg   = Reg(Vec(32, UInt(8.W))); upRegWire   := upReg
+    out := Cat( (0 until 4).map{i => downRegWire(i)}.reverse )
+    oe  := Cat( (4 until 8).map{i => downRegWire(i)}.reverse )
 
-trait LocalRegisters { this: BackBoardSlvBase =>
+    when( true.B ){
-  val led = IO(Output(UInt(3.W)))
+      for( i <- 0 until 4 ) {
-  val sw  = IO( Input(UInt(1.W)))
+        upReg(i) := in( i*8+7,8*i )
-
-
-
-  val digitalDir = RegInit(0.U(32.W))
-  val digitalOut = RegInit(0.U(32.W))
-  val digitalIn  = RegInit(VecInit(Seq.fill(32){false.B}))
-  val digitalFilter = RegInit(0.U(2.W))
-
-
-  val clk100usCnt = RegInit(0.U(13.W))
-
-  when( clk100usCnt < 5000.U ){
-    clk100usCnt := clk100usCnt + 1.U
-  } .otherwise{
-    clk100usCnt := 0.U
-  }
-
-  for( i <- 0 until 32 ) {
-    val hiCnt = RegInit( 0.U( 7.W ) )
-    val loCnt = RegInit( 0.U( 7.W ) )
-    val toCnt = RegInit( 0.U( 7.W ) )
-
-    when( digitalFilter === "b00".U ){
-      digitalIn(i) := sw
-    } .elsewhen( digitalFilter === "b01".U ){
-      when( clk100usCnt === 5000.U ){
-        when( toCnt === 10.U ){
-          hiCnt := 0.U
-          loCnt := 0.U
-          toCnt := 0.U
-          when( hiCnt >= 8.U & digitalIn(i) === false.B){ digitalIn(i) := true.B }
-          when( loCnt >= 8.U & digitalIn(i) === true.B) { digitalIn(i) := false.B }
-        } .elsewhen( toCnt > 10.U ){
-          hiCnt := 0.U
-          loCnt := 0.U
-          toCnt := 0.U
-        } .otherwise{
-          when(sw === true.B)  { hiCnt := hiCnt + 1.U }
-          when(sw === false.B) { loCnt := loCnt + 1.U }
-          toCnt := toCnt + 1.U
-        }
-      }
-    } .elsewhen( digitalFilter === "b10".U ){
-      when( clk100usCnt === 5000.U ){
-        when( toCnt === 40.U ){
-          hiCnt := 0.U
-          loCnt := 0.U
-          toCnt := 0.U
-          when( hiCnt >= 32.U & digitalIn(i) === false.B){ digitalIn(i) := true.B }
-          when( loCnt >= 32.U & digitalIn(i) === true.B) { digitalIn(i) := false.B }
-        } .elsewhen( toCnt > 40.U ){
-          hiCnt := 0.U
-          loCnt := 0.U
-          toCnt := 0.U
-        } .otherwise{
-          when(sw === true.B)  { hiCnt := hiCnt + 1.U }
-          when(sw === false.B) { loCnt := loCnt + 1.U }
-          toCnt := toCnt + 1.U
-        }
-      }
-    } .elsewhen( digitalFilter === "b11".U ){
-      when( clk100usCnt === 5000.U ){
-        when( toCnt === 80.U ){
-          hiCnt := 0.U
-          loCnt := 0.U
-          toCnt := 0.U
-          when( hiCnt >= 64.U & digitalIn(i) === false.B){ digitalIn(i) := true.B }
-          when( loCnt >= 64.U & digitalIn(i) === true.B) { digitalIn(i) := false.B }
-        } .elsewhen( toCnt > 80.U ){
-          hiCnt := 0.U
-          loCnt := 0.U
-          toCnt := 0.U
-        } .otherwise{
-          when(sw === true.B)  { hiCnt := hiCnt + 1.U }
-          when(sw === false.B) { loCnt := loCnt + 1.U }
-          toCnt := toCnt + 1.U
       }
     }
   }
-  }
-
-
-
-
-  
-  val pluseCnt = RegInit(0.U(32.W))
-
-  val pluseShift = ShiftRegisters( sw, 3, false.B, true.B )
-  when( ~pluseShift(2).asBool & pluseShift(1).asBool ){
-    pluseCnt := pluseCnt + 1.U
-  }
-
-  val pluseAutoCnt = RegInit(0.U(32.W))
-  val pluseAutoFre = RegInit(0.U(32.W))
-  when( clk100usCnt === 5000.U ){
-    pluseAutoCnt := 0.U
-    pluseAutoFre := pluseAutoCnt
-  } .elsewhen( ~pluseShift(2).asBool & pluseShift(1).asBool ){
-    pluseAutoCnt := pluseAutoCnt + 1.U
-  }
-
-  val qeiA = IO(Input(Bool()))
-  val qeiB = IO(Input(Bool()))
-
-  val qeiAShift = ShiftRegisters( qeiA, 2, false.B, true.B )
-  val qeiBShift = ShiftRegisters( qeiB, 3, false.B, true.B )
-
-  val qeiCnt = RegInit(0.U(32.W))
-  val qeiAutoCnt = RegInit(0.U(32.W))
-  val qeiAutoFre = RegInit(0.U(32.W))
-
-  when( ~qeiBShift(2) & qeiBShift(1) ){
-    qeiCnt := Mux( qeiAShift(1), qeiCnt + 1.U, qeiCnt - 1.U )
-    qeiAutoCnt := Mux( qeiAShift(1), qeiCnt + 1.U, qeiCnt - 1.U )
-  }
-
-
-  when( clk100usCnt === 5000.U ){
-    qeiAutoCnt := 0.U
-    qeiAutoFre := qeiAutoCnt
-  } .elsewhen( ~qeiBShift(2) & qeiBShift(1) ){
-    qeiAutoCnt := Mux( qeiAShift(1), qeiAutoCnt + 1.U, qeiAutoCnt - 1.U )
-  }
-  
-  
-  registersRD := Mux1H(Seq(
-    (upStreamReq.io.latDat.bits.register === 0.U) -> digitalDir,
-    (upStreamReq.io.latDat.bits.register === 1.U) -> digitalIn.asUInt,
-    (upStreamReq.io.latDat.bits.register === 2.U) -> digitalFilter,
-    (upStreamReq.io.latDat.bits.register === 3.U) -> pluseCnt,
-    (upStreamReq.io.latDat.bits.register === 4.U) -> pluseAutoFre,
-    (upStreamReq.io.latDat.bits.register === 5.U) -> qeiCnt,
-    (upStreamReq.io.latDat.bits.register === 6.U) -> qeiAutoFre,
-  ))
-
-  when( upStreamReq.io.latDat.fire & upStreamReq.io.latDat.bits.address(5,1) === io.localHost & upStreamReq.io.latDat.bits.address.extract(0) === 1.U ){
-    when(upStreamReq.io.latDat.bits.register === 0.U){
-      digitalDir := upStreamReq.io.latDat.bits.data
-    }
-    when(upStreamReq.io.latDat.bits.register === 1.U){
-      digitalOut := upStreamReq.io.latDat.bits.data
-    }
-    when(upStreamReq.io.latDat.bits.register === 2.U){
-      digitalFilter := upStreamReq.io.latDat.bits.data
-    }
-    when(upStreamReq.io.latDat.bits.register === 3.U){
-      pluseCnt := upStreamReq.io.latDat.bits.data
-    }
-    when(upStreamReq.io.latDat.bits.register === 4.U){
-      ;
-    }
-    when(upStreamReq.io.latDat.bits.register === 5.U){
-      qeiCnt := upStreamReq.io.latDat.bits.data
-    }
-    when(upStreamReq.io.latDat.bits.register === 6.U){
-      ;
-    }
-  }
-
-
-
-
-  led := digitalOut(2,0)
-  // digitalIn := sw
 }
+
+
+
+
+
+// trait LocalRegisters { this: BackBoardSlvBase =>
+//   val led = IO(Output(UInt(3.W)))
+//   val sw  = IO( Input(UInt(1.W)))
+
+
+
+//   val digitalDir = RegInit(0.U(32.W))
+//   val digitalOut = RegInit(0.U(32.W))
+//   val digitalIn  = RegInit(VecInit(Seq.fill(32){false.B}))
+//   val digitalFilter = RegInit(0.U(2.W))
+
+
+//   val clk100usCnt = RegInit(0.U(13.W))
+
+//   when( clk100usCnt < 5000.U ){
+//     clk100usCnt := clk100usCnt + 1.U
+//   } .otherwise{
+//     clk100usCnt := 0.U
+//   }
+
+//   for( i <- 0 until 32 ) {
+//     val hiCnt = RegInit( 0.U( 7.W ) )
+//     val loCnt = RegInit( 0.U( 7.W ) )
+//     val toCnt = RegInit( 0.U( 7.W ) )
+
+//     when( digitalFilter === "b00".U ){
+//       digitalIn(i) := sw
+//     } .elsewhen( digitalFilter === "b01".U ){
+//       when( clk100usCnt === 5000.U ){
+//         when( toCnt === 10.U ){
+//           hiCnt := 0.U
+//           loCnt := 0.U
+//           toCnt := 0.U
+//           when( hiCnt >= 8.U & digitalIn(i) === false.B){ digitalIn(i) := true.B }
+//           when( loCnt >= 8.U & digitalIn(i) === true.B) { digitalIn(i) := false.B }
+//         } .elsewhen( toCnt > 10.U ){
+//           hiCnt := 0.U
+//           loCnt := 0.U
+//           toCnt := 0.U
+//         } .otherwise{
+//           when(sw === true.B)  { hiCnt := hiCnt + 1.U }
+//           when(sw === false.B) { loCnt := loCnt + 1.U }
+//           toCnt := toCnt + 1.U
+//         }
+//       }
+//     } .elsewhen( digitalFilter === "b10".U ){
+//       when( clk100usCnt === 5000.U ){
+//         when( toCnt === 40.U ){
+//           hiCnt := 0.U
+//           loCnt := 0.U
+//           toCnt := 0.U
+//           when( hiCnt >= 32.U & digitalIn(i) === false.B){ digitalIn(i) := true.B }
+//           when( loCnt >= 32.U & digitalIn(i) === true.B) { digitalIn(i) := false.B }
+//         } .elsewhen( toCnt > 40.U ){
+//           hiCnt := 0.U
+//           loCnt := 0.U
+//           toCnt := 0.U
+//         } .otherwise{
+//           when(sw === true.B)  { hiCnt := hiCnt + 1.U }
+//           when(sw === false.B) { loCnt := loCnt + 1.U }
+//           toCnt := toCnt + 1.U
+//         }
+//       }
+//     } .elsewhen( digitalFilter === "b11".U ){
+//       when( clk100usCnt === 5000.U ){
+//         when( toCnt === 80.U ){
+//           hiCnt := 0.U
+//           loCnt := 0.U
+//           toCnt := 0.U
+//           when( hiCnt >= 64.U & digitalIn(i) === false.B){ digitalIn(i) := true.B }
+//           when( loCnt >= 64.U & digitalIn(i) === true.B) { digitalIn(i) := false.B }
+//         } .elsewhen( toCnt > 80.U ){
+//           hiCnt := 0.U
+//           loCnt := 0.U
+//           toCnt := 0.U
+//         } .otherwise{
+//           when(sw === true.B)  { hiCnt := hiCnt + 1.U }
+//           when(sw === false.B) { loCnt := loCnt + 1.U }
+//           toCnt := toCnt + 1.U
+//         }
+//       }
+//     }
+//   }
+
+
+
+
+  
+//   val pluseCnt = RegInit(0.U(32.W))
+
+//   val pluseShift = ShiftRegisters( sw, 3, false.B, true.B )
+//   when( ~pluseShift(2).asBool & pluseShift(1).asBool ){
+//     pluseCnt := pluseCnt + 1.U
+//   }
+
+//   val pluseAutoCnt = RegInit(0.U(32.W))
+//   val pluseAutoFre = RegInit(0.U(32.W))
+//   when( clk100usCnt === 5000.U ){
+//     pluseAutoCnt := 0.U
+//     pluseAutoFre := pluseAutoCnt
+//   } .elsewhen( ~pluseShift(2).asBool & pluseShift(1).asBool ){
+//     pluseAutoCnt := pluseAutoCnt + 1.U
+//   }
+
+//   val qeiA = IO(Input(Bool()))
+//   val qeiB = IO(Input(Bool()))
+
+//   val qeiAShift = ShiftRegisters( qeiA, 2, false.B, true.B )
+//   val qeiBShift = ShiftRegisters( qeiB, 3, false.B, true.B )
+
+//   val qeiCnt = RegInit(0.U(32.W))
+//   val qeiAutoCnt = RegInit(0.U(32.W))
+//   val qeiAutoFre = RegInit(0.U(32.W))
+
+//   when( ~qeiBShift(2) & qeiBShift(1) ){
+//     qeiCnt := Mux( qeiAShift(1), qeiCnt + 1.U, qeiCnt - 1.U )
+//     qeiAutoCnt := Mux( qeiAShift(1), qeiCnt + 1.U, qeiCnt - 1.U )
+//   }
+
+
+//   when( clk100usCnt === 5000.U ){
+//     qeiAutoCnt := 0.U
+//     qeiAutoFre := qeiAutoCnt
+//   } .elsewhen( ~qeiBShift(2) & qeiBShift(1) ){
+//     qeiAutoCnt := Mux( qeiAShift(1), qeiAutoCnt + 1.U, qeiAutoCnt - 1.U )
+//   }
+  
+  
+//   registersRD := Mux1H(Seq(
+//     (upStreamReq.io.latDat.bits.register === 0.U) -> digitalDir,
+//     (upStreamReq.io.latDat.bits.register === 1.U) -> digitalIn.asUInt,
+//     (upStreamReq.io.latDat.bits.register === 2.U) -> digitalFilter,
+//     (upStreamReq.io.latDat.bits.register === 3.U) -> pluseCnt,
+//     (upStreamReq.io.latDat.bits.register === 4.U) -> pluseAutoFre,
+//     (upStreamReq.io.latDat.bits.register === 5.U) -> qeiCnt,
+//     (upStreamReq.io.latDat.bits.register === 6.U) -> qeiAutoFre,
+//   ))
+
+//   when( upStreamReq.io.latDat.fire & upStreamReq.io.latDat.bits.address(5,1) === io.localHost & upStreamReq.io.latDat.bits.address.extract(0) === 1.U ){
+//     when(upStreamReq.io.latDat.bits.register === 0.U){
+//       digitalDir := upStreamReq.io.latDat.bits.data
+//     }
+//     when(upStreamReq.io.latDat.bits.register === 1.U){
+//       digitalOut := upStreamReq.io.latDat.bits.data
+//     }
+//     when(upStreamReq.io.latDat.bits.register === 2.U){
+//       digitalFilter := upStreamReq.io.latDat.bits.data
+//     }
+//     when(upStreamReq.io.latDat.bits.register === 3.U){
+//       pluseCnt := upStreamReq.io.latDat.bits.data
+//     }
+//     when(upStreamReq.io.latDat.bits.register === 4.U){
+//       ;
+//     }
+//     when(upStreamReq.io.latDat.bits.register === 5.U){
+//       qeiCnt := upStreamReq.io.latDat.bits.data
+//     }
+//     when(upStreamReq.io.latDat.bits.register === 6.U){
+//       ;
+//     }
+//   }
+
+
+
+
+//   led := digitalOut(2,0)
+//   // digitalIn := sw
+// }

src/test/scala/gcd/test.scala

@@ -17,12 +17,12 @@ object testModule extends App {
     ))
 
   (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-E", "verilog" ) ++ args, Seq(
-      ChiselGeneratorAnnotation(() => { new BackBoardSlv })
+      ChiselGeneratorAnnotation(() => { new BackBoardSlvDigitalIO })
     ))
 
-  (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-E", "verilog" ) ++ args, Seq(
+  // (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-E", "verilog" ) ++ args, Seq(
-      ChiselGeneratorAnnotation(() => { new BackPlaneChainTest })
+  //     ChiselGeneratorAnnotation(() => { new BackPlaneChainTest })
-    ))
+  //   ))
 
   // val cfg = new MacCfg