compile pass

2023-08-20 15:50:11 +08:00
parent f3a44f0b31
commit 589fc528a0
7 changed files with 204 additions and 171 deletions
--- a/src/test/scala/gcd/test.scala
+++ b/src/test/scala/gcd/test.scala
@@ -17,12 +17,12 @@ object testModule extends App {
    ))

  (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-E", "verilog" ) ++ args, Seq(
-      ChiselGeneratorAnnotation(() => { new BackBoardSlv })
+      ChiselGeneratorAnnotation(() => { new BackBoardSlvDigitalIO })
    ))

-  (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-E", "verilog" ) ++ args, Seq(
-      ChiselGeneratorAnnotation(() => { new BackPlaneChainTest })
-    ))
+  // (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-E", "verilog" ) ++ args, Seq(
+  //     ChiselGeneratorAnnotation(() => { new BackPlaneChainTest })
+  //   ))

  // val cfg = new MacCfg