compile pass

src/test/scala/gcd/BackPlaneChainTest.scala.bk

@@ -0,0 +1,87 @@
+package BACK
+
+import chisel3._
+import chisel3.util._
+
+class BackPlaneChainTestIO extends Bundle{
+
+  val clk400 = Input( Vec(6, Bool() ))
+
+
+
+
+  val spi = Flipped(Decoupled(new CDR_Master_Interface_Bundle))
+
+  val led = Output( Vec( 5, Bool() ) )
+
+
+}
+
+class BackPlaneChainTest extends Module{
+  val io: BackPlaneChainTestIO = IO(new BackPlaneChainTestIO)
+
+
+  val mst = Module(new BackBoardMst)
+  val slv = for( i <- 0 until 5 ) yield { Module(new BackBoardSlv) }
+
+
+
+  mst.io.clk4 := io.clk400(5)
+
+
+  withClockAndReset( io.clk400(5).asClock, reset.asAsyncReset ){
+    io.spi.ready := true.B
+    val cnt = RegInit(0.U(7.W))
+    val spiInfo = Reg( new CDR_Master_Interface_Bundle )
+    mst.io.MOSI := spiInfo.asUInt().extract( 6+8+32+2+16-1 )
+    val cs   = RegInit(true.B);  mst.io.CS   := cs
+    val sckCnt = RegInit(1.U(2.W)); mst.io.SCK := sckCnt.extract(1) === 1.U
+
+
+    when( ~cs ){
+      sckCnt := sckCnt + 1.U
+    }
+
+    when( io.spi.fire ){
+      cs := false.B
+      cnt := 0.U
+      spiInfo := io.spi.bits
+    } .elsewhen( cnt =/= 63.U & sckCnt === "b11".U ){
+      cnt := cnt + 1.U
+      spiInfo := Cat(spiInfo.asUInt( 6+8+32+2+16-2, 0 ), mst.io.MISO).asTypeOf(new CDR_Master_Interface_Bundle)
+    } .elsewhen( cnt === 63.U & sckCnt === "b11".U ){
+      cs := true.B
+    }
+  }
+
+
+  for( i <- 0 until 5 ) {
+    slv(i).io.localHost := i.U
+    slv(i).io.clk4 := io.clk400(i)
+
+    slv(i).sw := 0.U
+    slv(i).qeiA := false.B
+    slv(i).qeiB := false.B
+    io.led(i) := slv(i).led.extract(0).asBool
+
+  }
+
+
+  slv(0).io.upStreamReqDat := mst.io.downStreamRespdat
+  mst.io.downStreamReqDat  := slv(0).io.upStreamRespdat
+
+  slv(1).io.upStreamReqDat := slv(0).io.downStreamRespdat
+  slv(0).io.downStreamReqDat  := slv(1).io.upStreamRespdat
+
+  slv(2).io.upStreamReqDat := slv(1).io.downStreamRespdat
+  slv(1).io.downStreamReqDat  := slv(2).io.upStreamRespdat
+
+  slv(3).io.upStreamReqDat := slv(2).io.downStreamRespdat
+  slv(2).io.downStreamReqDat  := slv(3).io.upStreamRespdat
+
+  slv(4).io.upStreamReqDat := slv(3).io.downStreamRespdat
+  slv(3).io.downStreamReqDat  := slv(4).io.upStreamRespdat  
+
+ 
+  slv(4).io.downStreamReqDat := slv(4).io.downStreamRespdat
+}