compile pass

src/main/scala/backBoard/BackBoardSlv.scala

@@ -32,12 +32,12 @@ abstract class BackBoardSlvBase extends RawModule{
   
 
   lvdsSlv.io.lvds_down_din  := io.lvds_down_din 
-  lvdsSlv.io.lvds_down_dout := io.lvds_down_dout
+  io.lvds_down_dout := lvdsSlv.io.lvds_down_dout
   lvdsSlv.io.lvds_up_din    := io.lvds_up_din   
-  lvdsSlv.io.lvds_up_dout   := io.lvds_up_dout  
+  io.lvds_up_dout   := lvdsSlv.io.lvds_up_dout
     
-  val downReg = Reg(Vec(32, UInt(8.W)))
-  val upReg   = Reg(Vec(32, UInt(8.W)))
+  val downRegWire = Wire(Vec(32, UInt(8.W)))
+  val upRegWire   = Wire(Vec(32, UInt(8.W)))
 
 
 
@@ -50,8 +50,8 @@ abstract class BackBoardSlvBase extends RawModule{
   // val downstream_rx_cdr_err = Output(Bool())
   // val downstream_sync = Output(Bool())
 
-  val upstream_tx_data_ready = Output(Bool())
-  val upstream_tx_data_in = Input(UInt(8.W))
+  // val upstream_tx_data_ready = Output(Bool())
+  // val upstream_tx_data_in = Input(UInt(8.W))
 
   // val upstream_rx_crc_valid = Output(Bool())
   // val upstream_rx_crc_err = Output(Bool())
@@ -63,9 +63,13 @@ abstract class BackBoardSlvBase extends RawModule{
 trait BackBoardSlvDown{ this: BackBoardSlvBase =>
 
   withClockAndReset( io.ides_pclk.asClock, io.reset ){
+
+    val downReg = Reg(Vec(32, UInt(8.W))); downRegWire := downReg
+
+
     val downCnt = RegInit(0.U(6.W))
     val downTimeoutEn  = RegInit( false.B )
-    val downTimeoutRst = (downCnt === 0.U & downstream_rx_data_valid)
+    val downTimeoutRst = (downCnt === 0.U & lvdsSlv.io.downstream_rx_data_valid)
     val ( _, downTimeout ) = Counter( Range( 0,1023 ), downTimeoutEn, downTimeoutRst )
 
 
@@ -74,8 +78,8 @@ trait BackBoardSlvDown{ this: BackBoardSlvBase =>
         downReg(i) := 0.U
       }
     } .otherwise{
-      when( downstream_rx_data_valid ){
-        downReg(downCnt) := downstream_rx_data_out
+      when( lvdsSlv.io.downstream_rx_data_valid ){
+        downReg(downCnt) := lvdsSlv.io.downstream_rx_data_out
       }
     }
 
@@ -83,7 +87,7 @@ trait BackBoardSlvDown{ this: BackBoardSlvBase =>
       downTimeoutEn := false.B
     } .elsewhen( downCnt === 32.U ){
       downTimeoutEn := false.B
-    } .elsewhen(downCnt === 0.U & downstream_rx_data_valid){
+    } .elsewhen(downCnt === 0.U & lvdsSlv.io.downstream_rx_data_valid){
       downTimeoutEn := true.B
     }
 
@@ -91,7 +95,7 @@ trait BackBoardSlvDown{ this: BackBoardSlvBase =>
       downCnt := 0.U
     }.elsewhen( downCnt === 32.U ){
       downCnt := 0.U
-    }.elsewhen( downstream_rx_data_valid ){
+    }.elsewhen( lvdsSlv.io.downstream_rx_data_valid ){
       downCnt := downCnt + 1.U
     }
 
@@ -103,16 +107,18 @@ trait BackBoardSlvUp{ this: BackBoardSlvBase =>
   withClockAndReset( io.ides_pclk.asClock, io.reset ){
     val upCnt = RegInit(0.U(6.W))
     val upTimeoutEn  = RegInit( false.B )
-    val upTimeoutRst = (upCnt === 0.U & upstream_tx_data_ready)
+    val upTimeoutRst = (upCnt === 0.U & lvdsSlv.io.upstream_tx_data_ready)
     val ( _, upTimeout ) = Counter( Range( 0,1023 ), upTimeoutEn, upTimeoutRst )
 
+
+    lvdsSlv.io.upstream_tx_data_in := upRegWire(upCnt)
       // when( upstream_tx_data_ready ){
-      //   upstream_tx_data_ready := upReg(upCnt)
+      //   upstream_tx_data_ready := upRegWire(upCnt)
       // }
 
     when( io.reset ){
       for( i <- 0 until 32 ){
-        upReg(i) := 0.U
+        upRegWire(i) := 0.U
       }
     } .otherwise{
 
@@ -122,18 +128,20 @@ trait BackBoardSlvUp{ this: BackBoardSlvBase =>
       upTimeoutEn := false.B
     } .elsewhen( upCnt === 32.U ){
       upTimeoutEn := false.B
-    } .elsewhen(upCnt === 0.U & upstream_tx_data_ready){
+    } .elsewhen(upCnt === 32.U & lvdsSlv.io.upstream_tx_data_ready){
       upTimeoutEn := true.B
     }
 
     when( upTimeout ){
       upCnt := 0.U
-    }.elsewhen( upCnt === 32.U ){
+    }.elsewhen( upCnt === 32.U & lvdsSlv.io.upstream_tx_data_ready ){
       upCnt := 0.U
-    }.elsewhen( upstream_tx_data_ready ){
+    }.elsewhen( lvdsSlv.io.upstream_tx_data_ready ){
       upCnt := upCnt + 1.U
     }
 
   }
 }
 
+
+