compile pass

src/main/scala/backBoard/BackBoardMst.scala

@@ -5,7 +5,7 @@ import chisel3.util._
 
 class FSMC_Port_Bundle extends Bundle{
 
-  val addr    = Input(UInt(12.W))
+  val addr    = Input(UInt(13.W))
   val dataIn  = Input(UInt(8.W))
   val dataOut = Output(UInt(8.W))
   val dataOEn = Output(Bool())
@@ -38,8 +38,8 @@ class BackBoardMstBase extends RawModule{
   val mirrorDown = Module(new MirrorSRAM)
   val mirrorUp = Module(new MirrorSRAM)
 
-  val status  = Reg(UInt(8.W))
-  val slvNum  = Reg(UInt(5.W))
+    val status  = Wire(UInt(8.W))
+    val slvNum  = Wire(UInt(5.W))
 
 
   mirrorDown.io.clock := io.ides_pclk.asBool
@@ -54,6 +54,9 @@ class BackBoardMstBase extends RawModule{
 trait BackBoardMstFSMC{ this: BackBoardMstBase =>
 
   withClockAndReset( io.ides_pclk.asClock, io.reset ){
+    val statusReg = RegInit(0.U(8.W)); status := statusReg
+    val slvNumReg = RegInit(0.U(5.W)); slvNum := slvNumReg
+
     val fsmcAddrSync   = ShiftRegister( io.FSMC.addr,   2, 0.U, true.B )
     val fsmcdataInSync = ShiftRegister( io.FSMC.dataIn, 2, 0.U, true.B )
     val fsmcCEnSync    = ShiftRegister( io.FSMC.cen,    2, true.B, true.B )
@@ -82,11 +85,11 @@ trait BackBoardMstFSMC{ this: BackBoardMstBase =>
     ))
 
     when( (~fsmcCEnSync & fsmcAddrSync.extract(12) & (~fsmcWEnSync) ) & (fsmcAddrSync(10,0) === 0.U) ){
-      status := fsmcdataInSync
+      statusReg := fsmcdataInSync
     }
 
     when( (~fsmcCEnSync & fsmcAddrSync.extract(12) & (~fsmcWEnSync) ) & (fsmcAddrSync(10,0) === 1.U) ){
-      slvNum := fsmcdataInSync
+      slvNumReg := fsmcdataInSync
     }
 
   }
@@ -217,3 +220,5 @@ trait BackBoardMstLVDS{ this: BackBoardMstBase =>
 
 
 }
+
+class BackBoardMst extends BackBoardMstBase with BackBoardMstFSMC with BackBoardMstLVDS