撤销idle状态cdrout强制传输线为0的设定

src/main/scala/backBoard/ebus/CDROut.scala

@@ -62,12 +62,9 @@ class CDROut extends Module{
   }
 
 
-  when( stateCurr === STATE_IDLE ){
+
-    when( stateNext === STATE_PREAMBLE ){
+  when( stateCurr === STATE_IDLE & stateNext === STATE_PREAMBLE){ //PRE
     shiftData := ETH_PRE
-    } .elsewhen( stateNext === STATE_IDLE ){
-      shiftData := 0.U
-    }
   } .otherwise{
     when( bitCnt =/= 9.U ){
       shiftData := shiftData << 1