From 581c61401711b8b81255cf71db9abad283a8f75d Mon Sep 17 00:00:00 2001
From: Ruige Lee <wut.ruigeli@gmail.com>
Date: Thu, 17 Jul 2025 10:03:31 +0800
Subject: [PATCH] =?UTF-8?q?=E6=92=A4=E9=94=80idle=E7=8A=B6=E6=80=81cdrout?=
 =?UTF-8?q?=E5=BC=BA=E5=88=B6=E4=BC=A0=E8=BE=93=E7=BA=BF=E4=B8=BA0?=
 =?UTF-8?q?=E7=9A=84=E8=AE=BE=E5=AE=9A?=
MIME-Version: 1.0
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---
 src/main/scala/backBoard/ebus/CDROut.scala | 9 +++------
 1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/src/main/scala/backBoard/ebus/CDROut.scala b/src/main/scala/backBoard/ebus/CDROut.scala
index 363183d..3ff2a27 100644
--- a/src/main/scala/backBoard/ebus/CDROut.scala
+++ b/src/main/scala/backBoard/ebus/CDROut.scala
@@ -62,12 +62,9 @@ class CDROut extends Module{
   }
 
 
-  when( stateCurr === STATE_IDLE ){
-    when( stateNext === STATE_PREAMBLE ){
-      shiftData := ETH_PRE
-    } .elsewhen( stateNext === STATE_IDLE ){
-      shiftData := 0.U
-    }
+
+  when( stateCurr === STATE_IDLE & stateNext === STATE_PREAMBLE){ //PRE
+    shiftData := ETH_PRE
   } .otherwise{
     when( bitCnt =/= 9.U ){
       shiftData := shiftData << 1