中断模式软件完成

This commit is contained in:
RuigeLee
2024-10-29 09:33:29 +08:00
parent 7bcd0aaca0
commit 57c6c15c29
4 changed files with 5 additions and 4 deletions

View File

@@ -94,8 +94,8 @@ sw:
# riscv64-unknown-elf-objcopy --add-section .trap_entry=./tb/sw/build/test.bin ./tb/sw/build/test.elf ./tb/sw/build/test_with_section.elf
riscv64-unknown-elf-readelf -a ./tb/sw/build/test.elf
riscv64-unknown-elf-objcopy --add-section .trap_entry=./tb/sw/build/test.bin ./tb/sw/build/test.elf ./tb/sw/build/test_with_section.elf
# riscv64-unknown-elf-readelf -a ./tb/sw/build/test.elf
# riscv64-unknown-elf-objcopy --add-section .trap_entry=./tb/sw/build/test.bin ./tb/sw/build/test.elf ./tb/sw/build/test_with_section.elf
riscv64-unknown-elf-objcopy -O verilog ./tb/sw/build/test.elf ./tb/sw/build/test.verilog
sed -i 's/@800/@000/g' ./tb/sw/build/test.verilog

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@@ -33,6 +33,7 @@ BackSys s_BackSys(
initial begin
clock = 0;
reset = 1;
overCLK = 0;
#200

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@@ -30,7 +30,7 @@ main:
li x15, 0 #
lw x7, 0(x5) # cdr_0_tx_status
andi x7, x7, 0x2 # 11
beqz x7, 2b # 102
bnez x7, 2b # 102
3:
# cdr_0_tx_txFifo0x5532

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@@ -38,7 +38,7 @@ _prog_start:
.balign 32
.section .trap_entry
.section .trap_entry, "ax", %progbits
trap_entry:
# q0 return address
# q1 bitmask of all IRQ to be handled, may be more than one IRQ