diff --git a/Makefile b/Makefile
index 20be45c..f00b0a7 100644
--- a/Makefile
+++ b/Makefile
@@ -94,8 +94,8 @@ sw:
 
 	# riscv64-unknown-elf-objcopy  --add-section .trap_entry=./tb/sw/build/test.bin ./tb/sw/build/test.elf  ./tb/sw/build/test_with_section.elf
 	
-	riscv64-unknown-elf-readelf -a ./tb/sw/build/test.elf
-	riscv64-unknown-elf-objcopy --add-section .trap_entry=./tb/sw/build/test.bin ./tb/sw/build/test.elf ./tb/sw/build/test_with_section.elf
+	# riscv64-unknown-elf-readelf -a ./tb/sw/build/test.elf
+	# riscv64-unknown-elf-objcopy --add-section .trap_entry=./tb/sw/build/test.bin ./tb/sw/build/test.elf ./tb/sw/build/test_with_section.elf
 	riscv64-unknown-elf-objcopy -O verilog  ./tb/sw/build/test.elf  ./tb/sw/build/test.verilog
 	sed -i 's/@800/@000/g' ./tb/sw/build/test.verilog
 
diff --git a/tb/backSys_tb.v b/tb/backSys_tb.v
index d35606f..936c00d 100644
--- a/tb/backSys_tb.v
+++ b/tb/backSys_tb.v
@@ -33,6 +33,7 @@ BackSys s_BackSys(
 initial begin
 	clock = 0;
 	reset = 1;
+	overCLK = 0;
 
 	#200
 
diff --git a/tb/sw/src/main.S b/tb/sw/src/main.S
index 6ca28c7..acc1343 100644
--- a/tb/sw/src/main.S
+++ b/tb/sw/src/main.S
@@ -30,7 +30,7 @@ main:
 	li   x15, 0              # 清标志位
     lw   x7, 0(x5)           # 读取cdr_0_tx_status的值
     andi x7, x7, 0x2         # 检查第1比特（位1）
-    beqz x7, 2b              # 如果第1比特为0，则回到2处继续循环
+    bnez x7, 2b              # 如果第1比特不为0，则回到2处继续循环
 
 3:
     # 向cdr_0_tx_txFifo地址写入0x55，循环32次
diff --git a/tb/sw/src/startup.S b/tb/sw/src/startup.S
index 1e6ffa1..bd2dee0 100644
--- a/tb/sw/src/startup.S
+++ b/tb/sw/src/startup.S
@@ -38,7 +38,7 @@ _prog_start:
 
 
 .balign 32
-.section .trap_entry
+.section .trap_entry, "ax", %progbits
 trap_entry:
 	# q0 return address
 	# q1 bitmask of all IRQ to be handled, may be more than one IRQ