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中断模式软件完成

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RuigeLee
2024-10-29 09:33:29 +08:00
parent 7bcd0aaca0
commit 57c6c15c29
4 changed files with 5 additions and 4 deletions
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4
Makefile
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@@ -94,8 +94,8 @@ sw:
# riscv64-unknown-elf-objcopy --add-section .trap_entry=./tb/sw/build/test.bin ./tb/sw/build/test.elf ./tb/sw/build/test_with_section.elf # riscv64-unknown-elf-objcopy --add-section .trap_entry=./tb/sw/build/test.bin ./tb/sw/build/test.elf ./tb/sw/build/test_with_section.elf
riscv64-unknown-elf-readelf -a ./tb/sw/build/test.elf # riscv64-unknown-elf-readelf -a ./tb/sw/build/test.elf
riscv64-unknown-elf-objcopy --add-section .trap_entry=./tb/sw/build/test.bin ./tb/sw/build/test.elf ./tb/sw/build/test_with_section.elf # riscv64-unknown-elf-objcopy --add-section .trap_entry=./tb/sw/build/test.bin ./tb/sw/build/test.elf ./tb/sw/build/test_with_section.elf
riscv64-unknown-elf-objcopy -O verilog ./tb/sw/build/test.elf ./tb/sw/build/test.verilog riscv64-unknown-elf-objcopy -O verilog ./tb/sw/build/test.elf ./tb/sw/build/test.verilog
sed -i 's/@800/@000/g' ./tb/sw/build/test.verilog sed -i 's/@800/@000/g' ./tb/sw/build/test.verilog

1
tb/backSys_tb.v
View File

@@ -33,6 +33,7 @@ BackSys s_BackSys(
initial begin initial begin
clock = 0; clock = 0;
reset = 1; reset = 1;
overCLK = 0;
#200 #200

2
tb/sw/src/main.S
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@@ -30,7 +30,7 @@ main:
li x15, 0 # 清标志位 li x15, 0 # 清标志位
lw x7, 0(x5) # 读取cdr_0_tx_status的值 lw x7, 0(x5) # 读取cdr_0_tx_status的值
andi x7, x7, 0x2 # 检查第1比特（位1） andi x7, x7, 0x2 # 检查第1比特（位1）
beqz x7, 2b # 如果第1比特为0，则回到2处继续循环 bnez x7, 2b # 如果第1比特不为0，则回到2处继续循环
3: 3:
# 向cdr_0_tx_txFifo地址写入0x55，循环32次 # 向cdr_0_tx_txFifo地址写入0x55，循环32次

2
tb/sw/src/startup.S
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@@ -38,7 +38,7 @@ _prog_start:
.balign 32 .balign 32
.section .trap_entry .section .trap_entry, "ax", %progbits
trap_entry: trap_entry:
# q0 return address # q0 return address
# q1 bitmask of all IRQ to be handled, may be more than one IRQ # q1 bitmask of all IRQ to be handled, may be more than one IRQ