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主站发送的应该是加了offset的timestamp（reco）；softreset应该同步后输入异步口

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This commit is contained in:
Ruige Lee
2025-09-03 15:51:28 +08:00
parent f0beaf1571
commit 5776b9a7ad
2 changed files with 26 additions and 13 deletions
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16
src/main/scala/backBoard/shin/MasterParser.scala
View File

@@ -113,14 +113,14 @@ abstract class MasterParserBase extends Module with RequireAsyncReset{
io.downOut.bits.tdata := Mux1H(Seq( io.downOut.bits.tdata := Mux1H(Seq(
( txCnt < txLen ) -> ( txCnt < txLen ) ->
MuxCase( io.sram_r.datar, Array( MuxCase( io.sram_r.datar, Array(
( isRplTimeStamp & ( txCnt === rplCnt0 ) ) -> RegEnable(io.cReg.timeStamp(7,0), 0.U(8.W), io.downOut.fire & txCnt === 0.U ), ( isRplTimeStamp & ( txCnt === rplCnt0 ) ) -> RegEnable(io.cReg.recoTimeStamp(7,0), 0.U(8.W), io.downOut.fire & txCnt === 0.U ),
( isRplTimeStamp & ( txCnt === rplCnt1 ) ) -> RegEnable(io.cReg.timeStamp(15,8), 0.U(8.W), io.downOut.fire & txCnt === 0.U ), ( isRplTimeStamp & ( txCnt === rplCnt1 ) ) -> RegEnable(io.cReg.recoTimeStamp(15,8), 0.U(8.W), io.downOut.fire & txCnt === 0.U ),
( isRplTimeStamp & ( txCnt === rplCnt2 ) ) -> RegEnable(io.cReg.timeStamp(23,16), 0.U(8.W), io.downOut.fire & txCnt === 0.U ), ( isRplTimeStamp & ( txCnt === rplCnt2 ) ) -> RegEnable(io.cReg.recoTimeStamp(23,16), 0.U(8.W), io.downOut.fire & txCnt === 0.U ),
( isRplTimeStamp & ( txCnt === rplCnt3 ) ) -> RegEnable(io.cReg.timeStamp(31,24), 0.U(8.W), io.downOut.fire & txCnt === 0.U ), ( isRplTimeStamp & ( txCnt === rplCnt3 ) ) -> RegEnable(io.cReg.recoTimeStamp(31,24), 0.U(8.W), io.downOut.fire & txCnt === 0.U ),
( isRplTimeStamp & ( txCnt === rplCnt4 ) ) -> RegEnable(io.cReg.timeStamp(39,32), 0.U(8.W), io.downOut.fire & txCnt === 0.U ), ( isRplTimeStamp & ( txCnt === rplCnt4 ) ) -> RegEnable(io.cReg.recoTimeStamp(39,32), 0.U(8.W), io.downOut.fire & txCnt === 0.U ),
( isRplTimeStamp & ( txCnt === rplCnt5 ) ) -> RegEnable(io.cReg.timeStamp(47,40), 0.U(8.W), io.downOut.fire & txCnt === 0.U ), ( isRplTimeStamp & ( txCnt === rplCnt5 ) ) -> RegEnable(io.cReg.recoTimeStamp(47,40), 0.U(8.W), io.downOut.fire & txCnt === 0.U ),
( isRplTimeStamp & ( txCnt === rplCnt6 ) ) -> RegEnable(io.cReg.timeStamp(55,48), 0.U(8.W), io.downOut.fire & txCnt === 0.U ), ( isRplTimeStamp & ( txCnt === rplCnt6 ) ) -> RegEnable(io.cReg.recoTimeStamp(55,48), 0.U(8.W), io.downOut.fire & txCnt === 0.U ),
( isRplTimeStamp & ( txCnt === rplCnt7 ) ) -> RegEnable(io.cReg.timeStamp(63,56), 0.U(8.W), io.downOut.fire & txCnt === 0.U ), ( isRplTimeStamp & ( txCnt === rplCnt7 ) ) -> RegEnable(io.cReg.recoTimeStamp(63,56), 0.U(8.W), io.downOut.fire & txCnt === 0.U ),
( isRplDeltaStamp & ( txCnt === rplCnt8 ) ) -> io.cReg.mstDeltaTime(7,0), ( isRplDeltaStamp & ( txCnt === rplCnt8 ) ) -> io.cReg.mstDeltaTime(7,0),
( isRplDeltaStamp & ( txCnt === rplCnt9 ) ) -> io.cReg.mstDeltaTime(15,8), ( isRplDeltaStamp & ( txCnt === rplCnt9 ) ) -> io.cReg.mstDeltaTime(15,8),
( isRplDeltaStamp & ( txCnt === rplCnt10 ) ) -> io.cReg.mstDeltaTime(23,16), ( isRplDeltaStamp & ( txCnt === rplCnt10 ) ) -> io.cReg.mstDeltaTime(23,16),

23
tb/shinTest/ShinTopSpiTb.v
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@@ -102,15 +102,28 @@ module ShinTopSpiTb(
reg _reset_deactive; reg _reset_deactive;
wire [(`ALL_DEV_NUM - 1):0] isSoftReset; wire [(`ALL_DEV_NUM - 1):0] isSoftReset;
reg [(`ALL_DEV_NUM - 1):0] isSoftReset_reg;
generate
for( genvar i = 0; i < `ALL_DEV_NUM; i = i + 1 ) begin
always @(posedge clock or posedge reset) begin
if(reset) isSoftReset_reg[i] <= 1'b0;
else isSoftReset_reg[i] <= isSoftReset[i];
end
end
endgenerate
wire [`DEV_NUM:0] io_int_sig; wire [`DEV_NUM:0] io_int_sig;
reg latch0; reg latch0;
reg latch1; reg latch1;
ShinTop s_ShinTop_Mst( ShinTop s_ShinTop_Mst(
.clock(clock), .clock(clock),
.reset(reset | isSoftReset[0]), .reset(reset | isSoftReset_reg[0]),
.io_multiCLK_0(multiCLK[0]), .io_multiCLK_0(multiCLK[0]),
.io_multiCLK_1(multiCLK[1]), .io_multiCLK_1(multiCLK[1]),
@@ -165,7 +178,7 @@ ShinTop s_ShinTop_Mst(
`ifdef DEFINE_SLAVE_DEVICE `ifdef DEFINE_SLAVE_DEVICE
ShinTop s_ShinTop_slv0( ShinTop s_ShinTop_slv0(
.clock(clock), .clock(clock),
.reset(reset | isSoftReset[1]), .reset(reset | isSoftReset_reg[1]),
.io_multiCLK_0(multiCLK[0]), .io_multiCLK_0(multiCLK[0]),
.io_multiCLK_1(multiCLK[1]), .io_multiCLK_1(multiCLK[1]),
@@ -216,7 +229,7 @@ ShinTop s_ShinTop_slv0(
ShinTop s_ShinTop_slv1( ShinTop s_ShinTop_slv1(
.clock(clock), .clock(clock),
.reset(reset | isSoftReset[2]), .reset(reset | isSoftReset_reg[2]),
.io_multiCLK_0(multiCLK[0]), .io_multiCLK_0(multiCLK[0]),
.io_multiCLK_1(multiCLK[1]), .io_multiCLK_1(multiCLK[1]),
@@ -267,7 +280,7 @@ ShinTop s_ShinTop_slv1(
ShinTop s_ShinTop_slv2( ShinTop s_ShinTop_slv2(
.clock(clock), .clock(clock),
.reset(reset | isSoftReset[3]), .reset(reset | isSoftReset_reg[3]),
.io_multiCLK_0(multiCLK[0]), .io_multiCLK_0(multiCLK[0]),
.io_multiCLK_1(multiCLK[1]), .io_multiCLK_1(multiCLK[1]),
@@ -318,7 +331,7 @@ ShinTop s_ShinTop_slv2(
ShinTop s_ShinTop_slv3( ShinTop s_ShinTop_slv3(
.clock(clock), .clock(clock),
.reset(reset | isSoftReset[4]), .reset(reset | isSoftReset_reg[4]),
.io_multiCLK_0(multiCLK[0]), .io_multiCLK_0(multiCLK[0]),
.io_multiCLK_1(multiCLK[1]), .io_multiCLK_1(multiCLK[1]),