From 5776b9a7adac9b807ad1d8c939358018fb2f818b Mon Sep 17 00:00:00 2001 From: Ruige Lee Date: Wed, 3 Sep 2025 15:51:28 +0800 Subject: [PATCH] =?UTF-8?q?=E4=B8=BB=E7=AB=99=E5=8F=91=E9=80=81=E7=9A=84?= =?UTF-8?q?=E5=BA=94=E8=AF=A5=E6=98=AF=E5=8A=A0=E4=BA=86offset=E7=9A=84tim?= =?UTF-8?q?estamp=EF=BC=88reco=EF=BC=89=EF=BC=9Bsoftreset=E5=BA=94?= =?UTF-8?q?=E8=AF=A5=E5=90=8C=E6=AD=A5=E5=90=8E=E8=BE=93=E5=85=A5=E5=BC=82?= =?UTF-8?q?=E6=AD=A5=E5=8F=A3?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .../scala/backBoard/shin/MasterParser.scala | 16 ++++++------- tb/shinTest/ShinTopSpiTb.v | 23 +++++++++++++++---- 2 files changed, 26 insertions(+), 13 deletions(-) diff --git a/src/main/scala/backBoard/shin/MasterParser.scala b/src/main/scala/backBoard/shin/MasterParser.scala index eea465e..6bde127 100644 --- a/src/main/scala/backBoard/shin/MasterParser.scala +++ b/src/main/scala/backBoard/shin/MasterParser.scala @@ -113,14 +113,14 @@ abstract class MasterParserBase extends Module with RequireAsyncReset{ io.downOut.bits.tdata := Mux1H(Seq( ( txCnt < txLen ) -> MuxCase( io.sram_r.datar, Array( - ( isRplTimeStamp & ( txCnt === rplCnt0 ) ) -> RegEnable(io.cReg.timeStamp(7,0), 0.U(8.W), io.downOut.fire & txCnt === 0.U ), - ( isRplTimeStamp & ( txCnt === rplCnt1 ) ) -> RegEnable(io.cReg.timeStamp(15,8), 0.U(8.W), io.downOut.fire & txCnt === 0.U ), - ( isRplTimeStamp & ( txCnt === rplCnt2 ) ) -> RegEnable(io.cReg.timeStamp(23,16), 0.U(8.W), io.downOut.fire & txCnt === 0.U ), - ( isRplTimeStamp & ( txCnt === rplCnt3 ) ) -> RegEnable(io.cReg.timeStamp(31,24), 0.U(8.W), io.downOut.fire & txCnt === 0.U ), - ( isRplTimeStamp & ( txCnt === rplCnt4 ) ) -> RegEnable(io.cReg.timeStamp(39,32), 0.U(8.W), io.downOut.fire & txCnt === 0.U ), - ( isRplTimeStamp & ( txCnt === rplCnt5 ) ) -> RegEnable(io.cReg.timeStamp(47,40), 0.U(8.W), io.downOut.fire & txCnt === 0.U ), - ( isRplTimeStamp & ( txCnt === rplCnt6 ) ) -> RegEnable(io.cReg.timeStamp(55,48), 0.U(8.W), io.downOut.fire & txCnt === 0.U ), - ( isRplTimeStamp & ( txCnt === rplCnt7 ) ) -> RegEnable(io.cReg.timeStamp(63,56), 0.U(8.W), io.downOut.fire & txCnt === 0.U ), + ( isRplTimeStamp & ( txCnt === rplCnt0 ) ) -> RegEnable(io.cReg.recoTimeStamp(7,0), 0.U(8.W), io.downOut.fire & txCnt === 0.U ), + ( isRplTimeStamp & ( txCnt === rplCnt1 ) ) -> RegEnable(io.cReg.recoTimeStamp(15,8), 0.U(8.W), io.downOut.fire & txCnt === 0.U ), + ( isRplTimeStamp & ( txCnt === rplCnt2 ) ) -> RegEnable(io.cReg.recoTimeStamp(23,16), 0.U(8.W), io.downOut.fire & txCnt === 0.U ), + ( isRplTimeStamp & ( txCnt === rplCnt3 ) ) -> RegEnable(io.cReg.recoTimeStamp(31,24), 0.U(8.W), io.downOut.fire & txCnt === 0.U ), + ( isRplTimeStamp & ( txCnt === rplCnt4 ) ) -> RegEnable(io.cReg.recoTimeStamp(39,32), 0.U(8.W), io.downOut.fire & txCnt === 0.U ), + ( isRplTimeStamp & ( txCnt === rplCnt5 ) ) -> RegEnable(io.cReg.recoTimeStamp(47,40), 0.U(8.W), io.downOut.fire & txCnt === 0.U ), + ( isRplTimeStamp & ( txCnt === rplCnt6 ) ) -> RegEnable(io.cReg.recoTimeStamp(55,48), 0.U(8.W), io.downOut.fire & txCnt === 0.U ), + ( isRplTimeStamp & ( txCnt === rplCnt7 ) ) -> RegEnable(io.cReg.recoTimeStamp(63,56), 0.U(8.W), io.downOut.fire & txCnt === 0.U ), ( isRplDeltaStamp & ( txCnt === rplCnt8 ) ) -> io.cReg.mstDeltaTime(7,0), ( isRplDeltaStamp & ( txCnt === rplCnt9 ) ) -> io.cReg.mstDeltaTime(15,8), ( isRplDeltaStamp & ( txCnt === rplCnt10 ) ) -> io.cReg.mstDeltaTime(23,16), diff --git a/tb/shinTest/ShinTopSpiTb.v b/tb/shinTest/ShinTopSpiTb.v index 32dc4a7..5210667 100644 --- a/tb/shinTest/ShinTopSpiTb.v +++ b/tb/shinTest/ShinTopSpiTb.v @@ -102,15 +102,28 @@ module ShinTopSpiTb( reg _reset_deactive; wire [(`ALL_DEV_NUM - 1):0] isSoftReset; + reg [(`ALL_DEV_NUM - 1):0] isSoftReset_reg; + + generate + for( genvar i = 0; i < `ALL_DEV_NUM; i = i + 1 ) begin + always @(posedge clock or posedge reset) begin + if(reset) isSoftReset_reg[i] <= 1'b0; + else isSoftReset_reg[i] <= isSoftReset[i]; + end + end + endgenerate + wire [`DEV_NUM:0] io_int_sig; reg latch0; reg latch1; + + ShinTop s_ShinTop_Mst( .clock(clock), - .reset(reset | isSoftReset[0]), + .reset(reset | isSoftReset_reg[0]), .io_multiCLK_0(multiCLK[0]), .io_multiCLK_1(multiCLK[1]), @@ -165,7 +178,7 @@ ShinTop s_ShinTop_Mst( `ifdef DEFINE_SLAVE_DEVICE ShinTop s_ShinTop_slv0( .clock(clock), - .reset(reset | isSoftReset[1]), + .reset(reset | isSoftReset_reg[1]), .io_multiCLK_0(multiCLK[0]), .io_multiCLK_1(multiCLK[1]), @@ -216,7 +229,7 @@ ShinTop s_ShinTop_slv0( ShinTop s_ShinTop_slv1( .clock(clock), - .reset(reset | isSoftReset[2]), + .reset(reset | isSoftReset_reg[2]), .io_multiCLK_0(multiCLK[0]), .io_multiCLK_1(multiCLK[1]), @@ -267,7 +280,7 @@ ShinTop s_ShinTop_slv1( ShinTop s_ShinTop_slv2( .clock(clock), - .reset(reset | isSoftReset[3]), + .reset(reset | isSoftReset_reg[3]), .io_multiCLK_0(multiCLK[0]), .io_multiCLK_1(multiCLK[1]), @@ -318,7 +331,7 @@ ShinTop s_ShinTop_slv2( ShinTop s_ShinTop_slv3( .clock(clock), - .reset(reset | isSoftReset[4]), + .reset(reset | isSoftReset_reg[4]), .io_multiCLK_0(multiCLK[0]), .io_multiCLK_1(multiCLK[1]),