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bug上行测试完成

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This commit is contained in:
RuigeLee
2024-10-22 12:01:37 +08:00
parent 8950af8a47
commit 55d1e6e8e7
2 changed files with 64 additions and 34 deletions
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82
src/main/scala/backBoard/shin/ShinMst.scala
View File

@@ -49,8 +49,8 @@ abstract class ShinMstPhyBase extends Module{
val mirrorUp = Module(new MirrorSRAMDP())
val mirrorReg = Module(new MirrorSRAMDP())
val cdrOut = Module(new CDROut)
val cdrIn = Module(new CDRIn )
val cdrOut = Module(new CDROut with chisel3.util.experimental.InlineInstance)
val cdrIn = Module(new CDRIn with chisel3.util.experimental.InlineInstance)
io.serOut := cdrOut.io.serDat
cdrIn.io.serDat := io.serIn
@@ -128,7 +128,7 @@ trait ShinMstSend{ this: ShinMstPhyBase =>
sendStateNext := Mux1H(Seq(
(sendStateCurr === 0.U) -> Mux( isSendTrig, 1.U, 0.U ),
(sendStateCurr === 1.U) -> Mux( cdrOut.io.axis.fire & sendCntCurr === ((headByte)-1).U, 2.U, 1.U ),
(sendStateCurr === 1.U) -> Mux( cdrOut.io.axis.fire & sendCntCurr === (headByte-1).U, 2.U, 1.U ),
(sendStateCurr === 2.U) -> Mux( cdrOut.io.axis.fire & sendCntCurr === (sendHeader.length ) - 1.U, 3.U, 2.U ),
(sendStateCurr === 3.U) -> Mux( isRecvEnd | isTimeout, 0.U, 3.U ),
))
@@ -158,12 +158,23 @@ trait ShinMstSend{ this: ShinMstPhyBase =>
}
trait ShinMstRecv{ this: ShinMstPhyBase =>
val headByte: Int
def isSendTrig: Bool
val RecvStateIdle = 0.U
val RecvStateArm = 1.U
val RecvStateHead = 2.U
val RecvStatePayLoad = 3.U
val RecvStateCRC = 4.U
val RecvStateDeArm = 5.U
val recvStateNext = Wire( UInt(3.W) )
val recvStateCurr = RegNext( recvStateNext, 0.U )
val upPendBuf= Module( new Queue( new AXIS_Bundle(8), 2, pipe = true, flow = false ) with chisel3.util.experimental.InlineInstance )
cdrIn.io.axis <> upPendBuf.io.enq
val recvHeader = Reg( UInt( (new Header_Info_Bundle).getWidth.W) )
val recvCnt = Reg(UInt(10.W))
@@ -171,41 +182,60 @@ trait ShinMstRecv{ this: ShinMstPhyBase =>
val recvLength = recvHeader.asTypeOf(new Header_Info_Bundle).length
val isRecvEnd: Bool
isRecvEnd := recvStateCurr === 4.U
io.interrupt := recvStateCurr === 4.U
isRecvEnd := recvStateCurr === RecvStateDeArm
io.interrupt := recvStateCurr === RecvStateDeArm
recvStateNext := Mux1H(Seq(
(recvStateCurr === 0.U) -> Mux( isSendTrig, 1.U, 0.U ), //IDLE
(recvStateCurr === 1.U) -> Mux( cdrIn.io.axis.fire, 2.U, 1.U ), //Arm
(recvStateCurr === 2.U) -> Mux( cdrIn.io.axis.fire & recvCnt === ((recvHeader.getWidth/8-1)*2).U, 3.U, 2.U ), //Header
(recvStateCurr === 3.U) -> Mux( cdrIn.io.axis.fire & recvCnt === (recvLength), 4.U, 3.U ), //payload
(recvStateCurr === 4.U) -> 0.U, //de-Arm
(recvStateCurr === RecvStateIdle) -> Mux( isSendTrig, RecvStateArm, RecvStateIdle ), //IDLE
(recvStateCurr === RecvStateArm) -> Mux( upPendBuf.io.deq.valid, RecvStateHead, RecvStateArm ), //Arm
(recvStateCurr === RecvStateHead) -> Mux( upPendBuf.io.deq.fire, Mux( ~upPendBuf.io.deq.bits.tlast, Mux( recvCnt === (headByte-1).U, RecvStatePayLoad, RecvStateHead ), RecvStateDeArm ), RecvStateHead ), //Header
(recvStateCurr === RecvStatePayLoad) -> Mux( upPendBuf.io.deq.fire, Mux( ~upPendBuf.io.deq.bits.tlast, Mux( recvCnt === (recvLength-1.U), RecvStateCRC, RecvStatePayLoad ), RecvStateDeArm ), RecvStatePayLoad ), //payload
(recvStateCurr === RecvStateCRC) -> Mux( upPendBuf.io.deq.fire & upPendBuf.io.deq.bits.tlast, RecvStateDeArm, RecvStateCRC ),//crc
(recvStateCurr === RecvStateDeArm) -> RecvStateIdle,//de-arm
))
when( recvStateCurr === 0.U | recvStateCurr === 1.U | recvStateCurr === 4.U ){
when( recvStateCurr =/= recvStateNext ){
recvCnt := 0.U
} .elsewhen( recvStateCurr === 2.U | recvStateCurr === 3.U ){
when( cdrIn.io.axis.fire ){
recvCnt := Mux( recvStateCurr === recvStateNext, recvCnt + 1.U, 0.U )
} .elsewhen( upPendBuf.io.deq.fire ){
recvCnt := recvCnt + 1.U
}
when( upPendBuf.io.deq.fire & ( recvStateCurr === RecvStateHead )) {
recvHeader := Cat( recvHeader.tail(8), upPendBuf.io.deq.bits.tdata )
}
upPendBuf.io.deq.ready :=
recvStateCurr === RecvStateHead | recvStateCurr === RecvStatePayLoad | recvStateCurr === RecvStateCRC
val isRecvError = RegInit(false.B)
when( recvStateCurr === RecvStateIdle & recvStateNext === RecvStateArm ){
isRecvError := false.B
} .elsewhen( upPendBuf.io.deq.fire & upPendBuf.io.deq.bits.tuser ){
isRecvError := true.B
printf("Warning, Wrong Package Received in ShinMst, That could not happened!\n")
} .elsewhen( recvStateCurr === RecvStateHead & recvStateNext === RecvStateDeArm ){
isRecvError := true.B
printf("Warning, Wrong Package Received in ShinMst, That could not happened!\n")
} .elsewhen( recvStateCurr === RecvStatePayLoad & recvStateNext === RecvStateDeArm ){
isRecvError := true.B
printf("Warning, Wrong Package Received in ShinMst, That could not happened!\n")
} .elsewhen( recvStateCurr === RecvStateCRC & upPendBuf.io.deq.fire & upPendBuf.io.deq.bits.tlast & recvCnt =/= 3.U ){
isRecvError := true.B
printf("Warning, Wrong Package Received in ShinMst, That could not happened!\n")
}
when( cdrIn.io.axis.fire & ( recvStateCurr === 1.U | recvStateCurr === 2.U )) {
recvHeader := Cat( recvHeader.tail(8), cdrIn.io.axis.bits.tdata )
}
cdrIn.io.axis.ready :=
recvStateCurr === 1.U | recvStateCurr === 2.U | recvStateCurr === 3.U
val recvDataLatch = RegEnable( cdrIn.io.axis.bits.tdata, cdrIn.io.axis.fire & recvStateCurr === 3.U & recvCnt.extract(0) )
val recvDataLatch = RegEnable( upPendBuf.io.deq.bits.tdata, upPendBuf.io.deq.fire & recvStateCurr === 3.U & recvCnt.extract(0) )
mirrorUp.io.enrB := false.B
mirrorUp.io.enwB := cdrIn.io.axis.fire & recvStateCurr === 3.U & ~recvCnt.extract(0)
mirrorUp.io.datawB := Cat( cdrIn.io.axis.bits.tdata, recvDataLatch )
mirrorUp.io.enwB := upPendBuf.io.deq.fire & recvStateCurr === 3.U & ~recvCnt.extract(0)
mirrorUp.io.datawB := Cat( upPendBuf.io.deq.bits.tdata, recvDataLatch )
mirrorUp.io.addrB := recvCnt >> 1
val recvRamAddr = Reg(UInt(8.W))
@@ -233,7 +263,7 @@ trait ShinMstRecv{ this: ShinMstPhyBase =>
val isTimeout: Bool
isTimeout :=
Counter( Range(0, 20000000), enable = recvStateCurr === 1.U | recvStateCurr === 2.U | recvStateCurr === 3.U, reset = recvStateCurr === 0.U | recvStateCurr === 4.U )._2
Counter( Range(0, 20000000), enable = recvStateCurr === 1.U | recvStateCurr === 2.U | recvStateCurr === 3.U, reset = recvStateCurr === 0.U | recvStateCurr === 5.U )._2
}

18
src/main/scala/backBoard/shin/ShinSlv.scala
View File

@@ -25,11 +25,11 @@ class ShinSlvIO_Bundle extends Bundle{
abstract class ShinSlvPhyBase extends Module{
val io: ShinSlvIO_Bundle = IO(new ShinSlvIO_Bundle)
val downStreamCdrOut = Module(new CDROut)
val downStreamCdrIn = Module(new CDRIn )
val downStreamCdrOut = Module(new CDROut with chisel3.util.experimental.InlineInstance)
val downStreamCdrIn = Module(new CDRIn with chisel3.util.experimental.InlineInstance)
val upStreamCdrOut = Module(new CDROut)
val upStreamCdrIn = Module(new CDRIn )
val upStreamCdrOut = Module(new CDROut with chisel3.util.experimental.InlineInstance)
val upStreamCdrIn = Module(new CDRIn with chisel3.util.experimental.InlineInstance)
io.downSer.out := downStreamCdrOut.io.serDat
downStreamCdrIn.io.serDat := io.downSer.in
@@ -55,8 +55,8 @@ abstract class ShinSlvPhyBase extends Module{
val maxLocalByte = OpInitByte max OpBoardCastByte max OpUniCastByte
val downStreamFifo = Module( new Queue( new AXIS_Bundle(8), 8 + headByte + 4 ) )
val upStreamFifo = Module( new Queue( new AXIS_Bundle(8), headByte + maxLocalByte + 4 ) ) //4 is reserve
val downStreamFifo = Module( new Queue( new AXIS_Bundle(8), 8 + headByte + 4 ) with chisel3.util.experimental.InlineInstance)
val upStreamFifo = Module( new Queue( new AXIS_Bundle(8), headByte + maxLocalByte + 4 ) with chisel3.util.experimental.InlineInstance) //4 is reserve
val isLastDevice = Wire(Bool())
@@ -74,7 +74,7 @@ trait ShinSlvPhyDownStreamRecv{ this: ShinSlvPhyBase =>
val downOldHead = Reg( new Header_Info_Bundle )
val downNewHead = Reg( new Header_Info_Bundle )
val downPendBuf= Module( new Queue( new AXIS_Bundle(8), 2, pipe = true, flow = false ) )
val downPendBuf= Module( new Queue( new AXIS_Bundle(8), 2, pipe = true, flow = false ) with chisel3.util.experimental.InlineInstance)
downStreamCdrIn.io.axis <> downPendBuf.io.enq
val downRecvStateNext = Wire( UInt(3.W) )
@@ -241,7 +241,7 @@ trait ShinSlvPhyUpStreamRecv{ this: ShinSlvPhyDownStream =>
val upOldHead = Reg( new Header_Info_Bundle )
val upNewHead = Reg( new Header_Info_Bundle )
val upPendBuf= Module( new Queue( new AXIS_Bundle(8), 2, pipe = true, flow = false ) )
val upPendBuf= Module( new Queue( new AXIS_Bundle(8), 2, pipe = true, flow = false ) with chisel3.util.experimental.InlineInstance)
upStreamCdrIn.io.axis <> upPendBuf.io.enq
val upRecvStateNext = Wire( UInt(3.W) )
@@ -340,7 +340,7 @@ trait ShinSlvPhyUpStreamRecv{ this: ShinSlvPhyDownStream =>
} .elsewhen( upRecvStateCurr === UpRecvStateFData & upRecvStateNext === UpRecvStateIdle ){
isUpStreamError := true.B
printf("Warning, Wrong Package Received in UpStream, That could not happened!\n")
} .elsewhen( upRecvStateCurr === UpRecvStateCRC & (upRecvCnt > 3.U | (upPendBuf.io.deq.fire & upPendBuf.io.deq.bits.tlast & upRecvCnt < 3.U)) ){
} .elsewhen( upRecvStateCurr === UpRecvStateCRC & upPendBuf.io.deq.fire & upPendBuf.io.deq.bits.tlast & upRecvCnt =/= 3.U ){
isUpStreamError := true.B
printf("Warning, Wrong Package Received in UpStream, That could not happened!\n")
}