ruige/eb001
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

bug上行测试完成

Browse Source
This commit is contained in:
RuigeLee
2024-10-22 12:01:37 +08:00
parent 8950af8a47
commit 55d1e6e8e7
2 changed files with 64 additions and 34 deletions
Download Patch File Download Diff File Expand all files Collapse all files

18
src/main/scala/backBoard/shin/ShinSlv.scala
View File

@@ -25,11 +25,11 @@ class ShinSlvIO_Bundle extends Bundle{
abstract class ShinSlvPhyBase extends Module{
val io: ShinSlvIO_Bundle = IO(new ShinSlvIO_Bundle)
val downStreamCdrOut = Module(new CDROut)
val downStreamCdrIn = Module(new CDRIn )
val downStreamCdrOut = Module(new CDROut with chisel3.util.experimental.InlineInstance)
val downStreamCdrIn = Module(new CDRIn with chisel3.util.experimental.InlineInstance)
val upStreamCdrOut = Module(new CDROut)
val upStreamCdrIn = Module(new CDRIn )
val upStreamCdrOut = Module(new CDROut with chisel3.util.experimental.InlineInstance)
val upStreamCdrIn = Module(new CDRIn with chisel3.util.experimental.InlineInstance)
io.downSer.out := downStreamCdrOut.io.serDat
downStreamCdrIn.io.serDat := io.downSer.in
@@ -55,8 +55,8 @@ abstract class ShinSlvPhyBase extends Module{
val maxLocalByte = OpInitByte max OpBoardCastByte max OpUniCastByte
val downStreamFifo = Module( new Queue( new AXIS_Bundle(8), 8 + headByte + 4 ) )
val upStreamFifo = Module( new Queue( new AXIS_Bundle(8), headByte + maxLocalByte + 4 ) ) //4 is reserve
val downStreamFifo = Module( new Queue( new AXIS_Bundle(8), 8 + headByte + 4 ) with chisel3.util.experimental.InlineInstance)
val upStreamFifo = Module( new Queue( new AXIS_Bundle(8), headByte + maxLocalByte + 4 ) with chisel3.util.experimental.InlineInstance) //4 is reserve
val isLastDevice = Wire(Bool())
@@ -74,7 +74,7 @@ trait ShinSlvPhyDownStreamRecv{ this: ShinSlvPhyBase =>
val downOldHead = Reg( new Header_Info_Bundle )
val downNewHead = Reg( new Header_Info_Bundle )
val downPendBuf= Module( new Queue( new AXIS_Bundle(8), 2, pipe = true, flow = false ) )
val downPendBuf= Module( new Queue( new AXIS_Bundle(8), 2, pipe = true, flow = false ) with chisel3.util.experimental.InlineInstance)
downStreamCdrIn.io.axis <> downPendBuf.io.enq
val downRecvStateNext = Wire( UInt(3.W) )
@@ -241,7 +241,7 @@ trait ShinSlvPhyUpStreamRecv{ this: ShinSlvPhyDownStream =>
val upOldHead = Reg( new Header_Info_Bundle )
val upNewHead = Reg( new Header_Info_Bundle )
val upPendBuf= Module( new Queue( new AXIS_Bundle(8), 2, pipe = true, flow = false ) )
val upPendBuf= Module( new Queue( new AXIS_Bundle(8), 2, pipe = true, flow = false ) with chisel3.util.experimental.InlineInstance)
upStreamCdrIn.io.axis <> upPendBuf.io.enq
val upRecvStateNext = Wire( UInt(3.W) )
@@ -340,7 +340,7 @@ trait ShinSlvPhyUpStreamRecv{ this: ShinSlvPhyDownStream =>
} .elsewhen( upRecvStateCurr === UpRecvStateFData & upRecvStateNext === UpRecvStateIdle ){
isUpStreamError := true.B
printf("Warning, Wrong Package Received in UpStream, That could not happened!\n")
} .elsewhen( upRecvStateCurr === UpRecvStateCRC & (upRecvCnt > 3.U | (upPendBuf.io.deq.fire & upPendBuf.io.deq.bits.tlast & upRecvCnt < 3.U)) ){
} .elsewhen( upRecvStateCurr === UpRecvStateCRC & upPendBuf.io.deq.fire & upPendBuf.io.deq.bits.tlast & upRecvCnt =/= 3.U ){
isUpStreamError := true.B
printf("Warning, Wrong Package Received in UpStream, That could not happened!\n")
}