ruige/eb001
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

编译完成，bug:1 tx 最后一个字节读取了两次，2 先tx无法rx

Browse Source
This commit is contained in:
RuigeLee
2023-10-26 14:59:31 +08:00
parent 694d3890b0
commit 530e6d9792
3 changed files with 7 additions and 14 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
src/main/scala/Switch/MacRegisters.scala
View File

@@ -209,8 +209,8 @@ class MacRegImp(outer: MacReg)(implicit p: Parameters) extends LazyModuleImp(out
( 6 << 2 ) -> ( 6 << 2 ) ->
RegFieldGroup("PACKETLEN", Some("Packet Length Register"), Seq( RegFieldGroup("PACKETLEN", Some("Packet Length Register"), Seq(
RegField.r(16, 0.U, RegFieldDesc("maxFL", "Maximum Frame Length", reset=Some(0x0600))) ++ RegField.r(16, 0.U, RegFieldDesc("maxFL", "Maximum Frame Length", reset=Some(0x0600))),
RegField.r(16, 64.U, RegFieldDesc("minFL", "Minimum Frame Length", reset=Some(0x0040))) RegField.r(16, 64.U, RegFieldDesc("minFL", "Minimum Frame Length", reset=Some(0x0040))),
)), )),
( 7 << 2 ) -> ( 7 << 2 ) ->
RegFieldGroup("COLLCONF", Some("Collision and Retry Configuration Register"), Seq( RegFieldGroup("COLLCONF", Some("Collision and Retry Configuration Register"), Seq(
@@ -269,12 +269,12 @@ class MacRegImp(outer: MacReg)(implicit p: Parameters) extends LazyModuleImp(out
( 16 << 2 ) -> ( 16 << 2 ) ->
RegFieldGroup("MAC_ADDR0", Some("MAC Address Register 0"), Seq( RegFieldGroup("MAC_ADDR0", Some("MAC Address Register 0"), Seq(
RegField.r(1) RegField(32)
)), )),
( 17 << 2 ) -> ( 17 << 2 ) ->
RegFieldGroup("MAC_ADDR1", Some("MAC Address Register 1"), Seq( RegFieldGroup("MAC_ADDR1", Some("MAC Address Register 1"), Seq(
RegField.r(1) RegField(32)
)), )),
( 18 << 2 ) -> ( 18 << 2 ) ->
@@ -289,7 +289,7 @@ class MacRegImp(outer: MacReg)(implicit p: Parameters) extends LazyModuleImp(out
( 20 << 2 ) -> ( 20 << 2 ) ->
RegFieldGroup("TXCTRL", Some("Tx Control Register"), Seq( RegFieldGroup("TXCTRL", Some("Tx Control Register"), Seq(
RegField.r(8, 0,U, RegFieldDesc("TxPauseTV", "Tx Pause Timer Value", reset=Some(0x0))), RegField.r(8, 0.U, RegFieldDesc("TxPauseTV", "Tx Pause Timer Value", reset=Some(0x0))),
RegField.r(1, 0.U, RegFieldDesc("TxPauseRQ", "Tx Pause Request", reset=Some(0x0))), RegField.r(1, 0.U, RegFieldDesc("TxPauseRQ", "Tx Pause Request", reset=Some(0x0))),
)), )),

2
src/main/scala/Switch/mac/MAC.scala
View File

@@ -339,7 +339,7 @@ io.mii.mtxd_pad_o := txethmac.io.MTxD
io.mii.mtxen_pad_o := txethmac.io.MTxEn io.mii.mtxen_pad_o := txethmac.io.MTxEn
io.mii.mtxerr_pad_o := txethmac.io.MTxErr io.mii.mtxerr_pad_o := txethmac.io.MTxErr
TxDone := txethmac.io.TxDone TxDone := txethmac.io.TxDone
TxAbortIn := txethmac.io.TxAbort TxAbort := txethmac.io.TxAbort
TxUsedData := txethmac.io.TxUsedData TxUsedData := txethmac.io.TxUsedData
WillTransmit := txethmac.io.WillTransmit WillTransmit := txethmac.io.WillTransmit
ResetCollision := txethmac.io.ResetCollision ResetCollision := txethmac.io.ResetCollision

9
src/main/scala/Switch/mac/MacTx.scala
View File

@@ -14,7 +14,6 @@ class MacTxIO extends Bundle{
val CrcEn = Input(Bool()) // Crc enable (from register) val CrcEn = Input(Bool()) // Crc enable (from register)
val FullD = Input(Bool()) // Full duplex (from register) val FullD = Input(Bool()) // Full duplex (from register)
val DlyCrcEn = Input(Bool()) // Delayed Crc enabled (from register)
val IPGT = Input(UInt(7.W)) // Back to back transmit inter packet gap parameter (from register) val IPGT = Input(UInt(7.W)) // Back to back transmit inter packet gap parameter (from register)
val IPGR1 = Input(UInt(7.W)) // Non back to back transmit inter packet gap parameter IPGR1 (from register) val IPGR1 = Input(UInt(7.W)) // Non back to back transmit inter packet gap parameter IPGR1 (from register)
val IPGR2 = Input(UInt(7.W)) // Non back to back transmit inter packet gap parameter IPGR2 (from register) val IPGR2 = Input(UInt(7.W)) // Non back to back transmit inter packet gap parameter IPGR2 (from register)
@@ -74,7 +73,6 @@ abstract class MacTxBase extends Module with RequireAsyncReset{
val Rule1 = RegInit(false.B) val Rule1 = RegInit(false.B)
val ColWindow = RegInit(true.B) val ColWindow = RegInit(true.B)
val DlyCrcCnt = RegInit(0.U(3.W)) // Delayed CRC counter
val PacketFinished_q = RegInit(false.B) val PacketFinished_q = RegInit(false.B)
val ByteCnt = RegInit(0.U(16.W)) // Transmit Byte Counter val ByteCnt = RegInit(0.U(16.W)) // Transmit Byte Counter
val NibCnt = RegInit(0.U(16.W)) // Nibble Counter val NibCnt = RegInit(0.U(16.W)) // Nibble Counter
@@ -211,11 +209,6 @@ trait MacTxCounter { this: MacTxBase =>
ByteCnt := ByteCnt + 1.U ByteCnt := ByteCnt + 1.U
} }
when((StateData(1) & DlyCrcCnt === 4.U) | StartJam | PacketFinished_q){
DlyCrcCnt := 0.U
}.elsewhen(io.DlyCrcEn & (StateSFD | StateData(1) & (DlyCrcCnt.orR))){
DlyCrcCnt := DlyCrcCnt + 1.U
}
} }
@@ -223,7 +216,7 @@ trait MacTxCounter { this: MacTxBase =>
trait MacTxCRC{ this: MacTxBase => trait MacTxCRC{ this: MacTxBase =>
val Initialize_Crc = StateIdle | StatePreamble | (DlyCrcCnt.orR) val Initialize_Crc = StateIdle | StatePreamble
val Enable_Crc = ~StateFCS val Enable_Crc = ~StateFCS
val Data_Crc = val Data_Crc =