diff --git a/src/main/scala/Switch/MacRegisters.scala b/src/main/scala/Switch/MacRegisters.scala
index ceef532..a108086 100644
--- a/src/main/scala/Switch/MacRegisters.scala
+++ b/src/main/scala/Switch/MacRegisters.scala
@@ -209,8 +209,8 @@ class MacRegImp(outer: MacReg)(implicit p: Parameters) extends LazyModuleImp(out
 
       ( 6 << 2 ) ->
         RegFieldGroup("PACKETLEN", Some("Packet Length Register"), Seq(
-          RegField.r(16, 0.U, RegFieldDesc("maxFL", "Maximum Frame Length", reset=Some(0x0600))) ++
-          RegField.r(16, 64.U, RegFieldDesc("minFL", "Minimum Frame Length", reset=Some(0x0040)))
+          RegField.r(16, 0.U, RegFieldDesc("maxFL", "Maximum Frame Length", reset=Some(0x0600))),
+          RegField.r(16, 64.U, RegFieldDesc("minFL", "Minimum Frame Length", reset=Some(0x0040))),
         )),
       ( 7 << 2 ) ->
         RegFieldGroup("COLLCONF", Some("Collision and Retry Configuration Register"), Seq(
@@ -269,12 +269,12 @@ class MacRegImp(outer: MacReg)(implicit p: Parameters) extends LazyModuleImp(out
 
       ( 16 << 2 ) ->
         RegFieldGroup("MAC_ADDR0", Some("MAC Address Register 0"), Seq(
-          RegField.r(1)
+          RegField(32)
         )),
 
       ( 17 << 2 ) ->
         RegFieldGroup("MAC_ADDR1", Some("MAC Address Register 1"), Seq(
-          RegField.r(1)
+          RegField(32)
         )),
 
       ( 18 << 2 ) ->
@@ -289,7 +289,7 @@ class MacRegImp(outer: MacReg)(implicit p: Parameters) extends LazyModuleImp(out
         
       ( 20 << 2 ) ->
         RegFieldGroup("TXCTRL", Some("Tx Control Register"), Seq(
-          RegField.r(8, 0,U, RegFieldDesc("TxPauseTV", "Tx Pause Timer Value", reset=Some(0x0))), 
+          RegField.r(8, 0.U, RegFieldDesc("TxPauseTV", "Tx Pause Timer Value", reset=Some(0x0))), 
           RegField.r(1, 0.U, RegFieldDesc("TxPauseRQ", "Tx Pause Request", reset=Some(0x0))),
         )),
 
diff --git a/src/main/scala/Switch/mac/MAC.scala b/src/main/scala/Switch/mac/MAC.scala
index 11b862d..6adedad 100644
--- a/src/main/scala/Switch/mac/MAC.scala
+++ b/src/main/scala/Switch/mac/MAC.scala
@@ -339,7 +339,7 @@ io.mii.mtxd_pad_o    := txethmac.io.MTxD
 io.mii.mtxen_pad_o   := txethmac.io.MTxEn
 io.mii.mtxerr_pad_o := txethmac.io.MTxErr
 TxDone := txethmac.io.TxDone
-TxAbortIn := txethmac.io.TxAbort
+TxAbort := txethmac.io.TxAbort
 TxUsedData := txethmac.io.TxUsedData
 WillTransmit := txethmac.io.WillTransmit
 ResetCollision := txethmac.io.ResetCollision
diff --git a/src/main/scala/Switch/mac/MacTx.scala b/src/main/scala/Switch/mac/MacTx.scala
index a62cc95..e86712e 100644
--- a/src/main/scala/Switch/mac/MacTx.scala
+++ b/src/main/scala/Switch/mac/MacTx.scala
@@ -14,7 +14,6 @@ class MacTxIO extends Bundle{
 
   val CrcEn           = Input(Bool())         // Crc enable (from register)
   val FullD           = Input(Bool())         // Full duplex (from register)
-  val DlyCrcEn        = Input(Bool())         // Delayed Crc enabled (from register)
   val IPGT            = Input(UInt(7.W))         // Back to back transmit inter packet gap parameter (from register)
   val IPGR1           = Input(UInt(7.W))         // Non back to back transmit inter packet gap parameter IPGR1 (from register)
   val IPGR2           = Input(UInt(7.W))         // Non back to back transmit inter packet gap parameter IPGR2 (from register)
@@ -74,7 +73,6 @@ abstract class MacTxBase extends Module with RequireAsyncReset{
   val Rule1 = RegInit(false.B)
 
   val ColWindow = RegInit(true.B)
-  val DlyCrcCnt = RegInit(0.U(3.W)) // Delayed CRC counter
   val PacketFinished_q = RegInit(false.B)
   val ByteCnt = RegInit(0.U(16.W)) // Transmit Byte Counter
   val NibCnt = RegInit(0.U(16.W)) // Nibble Counter
@@ -211,11 +209,6 @@ trait MacTxCounter { this: MacTxBase =>
     ByteCnt := ByteCnt + 1.U
   }
        
-  when((StateData(1) & DlyCrcCnt === 4.U) | StartJam | PacketFinished_q){
-    DlyCrcCnt := 0.U
-  }.elsewhen(io.DlyCrcEn & (StateSFD | StateData(1) & (DlyCrcCnt.orR))){
-    DlyCrcCnt := DlyCrcCnt + 1.U
-  }
 
 }
 
@@ -223,7 +216,7 @@ trait MacTxCounter { this: MacTxBase =>
 
 trait MacTxCRC{ this: MacTxBase =>
 
-  val Initialize_Crc = StateIdle | StatePreamble | (DlyCrcCnt.orR)
+  val Initialize_Crc = StateIdle | StatePreamble
   val Enable_Crc = ~StateFCS
 
   val Data_Crc =