ruige/eb001
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

spi 成功触发主机发送

Browse Source
This commit is contained in:
Ruige Lee
2025-05-13 10:31:35 +08:00
parent 20b94fbe44
commit 51f941a8a6
2 changed files with 23 additions and 16 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
src/main/scala/backBoard/shin/SpiInterface.scala
View File

@@ -70,9 +70,9 @@ class SpiInterface extends Module{
// spiRegUp.io.enw := isSckPosedgeNext(1) & ~shiftCSn(1+1) & bitSel === 0.U & spiCmd === 1.U
io.isEnR := isSckPosedgeNext(0) & bitSel === 0.U & byteSel >= 3.U & isSpiRead
io.isEnW := isSckPosedgeNext(1) & ~shiftCSn(1+1) & bitSel === 0.U & isSpiWrite & byteSel >= 4.U
io.dataw := exReg
io.isEnR := isSckPosedge & ~shiftCSn(1+1) & bitSel === 7.U & byteSel >= 3.U & isSpiRead
io.isEnW := isSckPosedgeNext(0) & ~shiftCSn(1+1) & bitSel === 0.U & isSpiWrite & byteSel >= 4.U
io.dataw := RegNext(exReg)
when( shiftCSn(2) & ~shiftCSn(1) ){
bitSel := 0.U
@@ -86,9 +86,9 @@ class SpiInterface extends Module{
when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳
addrSel := 0.U
} .elsewhen(isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel === 0.U & byteSel === 1.U){ //CS为低，且SCK上跳的第0byte
} .elsewhen(isSckPosedge & ~shiftCSn(1) & bitSel === 7.U & byteSel === 0.U){ //CS为低，且SCK上跳的第0byte
addrSel := exReg
} .elsewhen(isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel === 0.U & byteSel === 2.U) {//CS为低，且SCK上跳的第0byte
} .elsewhen(isSckPosedge & ~shiftCSn(1) & bitSel === 7.U & byteSel === 1.U) {//CS为低，且SCK上跳的第0byte
addrSel := Cat(exReg, addrSel(7,0))
} .otherwise{ // byteSel > 1.U
when( isSckPosedge & byteSel > 3.U & bitSel === 7.U ){