diff --git a/src/main/scala/backBoard/shin/SpiInterface.scala b/src/main/scala/backBoard/shin/SpiInterface.scala
index b8b0008..d9121e4 100644
--- a/src/main/scala/backBoard/shin/SpiInterface.scala
+++ b/src/main/scala/backBoard/shin/SpiInterface.scala
@@ -70,9 +70,9 @@ class SpiInterface extends Module{
      
 //   spiRegUp.io.enw   := isSckPosedgeNext(1) & ~shiftCSn(1+1) & bitSel === 0.U & spiCmd === 1.U
 
-    io.isEnR := isSckPosedgeNext(0) & bitSel === 0.U & byteSel >= 3.U & isSpiRead
-    io.isEnW := isSckPosedgeNext(1) & ~shiftCSn(1+1) & bitSel === 0.U & isSpiWrite & byteSel >= 4.U
-    io.dataw := exReg
+    io.isEnR := isSckPosedge & ~shiftCSn(1+1) & bitSel === 7.U & byteSel >= 3.U & isSpiRead
+    io.isEnW := isSckPosedgeNext(0) & ~shiftCSn(1+1) & bitSel === 0.U & isSpiWrite & byteSel >= 4.U
+    io.dataw := RegNext(exReg)
 
   when( shiftCSn(2) & ~shiftCSn(1) ){
     bitSel   := 0.U
@@ -86,9 +86,9 @@ class SpiInterface extends Module{
 
   when( shiftCSn(2) & ~shiftCSn(1) ){  //CS下跳
     addrSel := 0.U
-  } .elsewhen(isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel === 0.U & byteSel === 1.U){ //CS为低，且SCK上跳的第0byte
+  } .elsewhen(isSckPosedge & ~shiftCSn(1) & bitSel === 7.U & byteSel === 0.U){ //CS为低，且SCK上跳的第0byte
     addrSel := exReg
-  } .elsewhen(isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel === 0.U & byteSel === 2.U) {//CS为低，且SCK上跳的第0byte
+  } .elsewhen(isSckPosedge & ~shiftCSn(1) & bitSel === 7.U & byteSel === 1.U) {//CS为低，且SCK上跳的第0byte
     addrSel := Cat(exReg, addrSel(7,0))
   } .otherwise{ // byteSel > 1.U
     when( isSckPosedge & byteSel > 3.U & bitSel === 7.U ){
diff --git a/tb/shinTest/ShinTopSpiTb.v b/tb/shinTest/ShinTopSpiTb.v
index 3ec7ed0..3f21bb5 100644
--- a/tb/shinTest/ShinTopSpiTb.v
+++ b/tb/shinTest/ShinTopSpiTb.v
@@ -17,7 +17,7 @@ module ShinTopSpiTb(
     wire spi_miso;
     reg [4:0] spi_csn;
 
-
+    wire isResp;
 
 ShinTop s_ShinTop_Mst(
   .clock(clock),
@@ -34,7 +34,7 @@ ShinTop s_ShinTop_Mst(
   .io_ospi_miso(spi_miso),
   .io_ospi_csn (spi_csn[0]),
 
-  .io_rsp_valid(),
+  .io_rsp_valid(isResp),
   .io_rsp_bits_isError(),
   .io_rsp_bits_length()
 );
@@ -218,11 +218,11 @@ end
 
   reg [11:0] transCnt;
   reg [11:0] byteCnt;
-  reg [3:0] bitCnt;
+  reg [2:0] bitCnt;
 
 
-always @(posedge sck) begin
-  if( isReq ) begin
+always @(posedge clock) begin
+  if( isReq & sck == 0 ) begin
     isBusy   <= #5 1'b1;
     transCnt <= #5 0;
 
@@ -232,12 +232,17 @@ always @(posedge sck) begin
     spi_csn[idx] <= #5 1'b0;
     exChangeReg <= txBuf[0];
   end
+end
 
+
+always @(posedge sck) begin
   if( isBusy ) begin
     if( transCnt < length ) begin
       bitCnt <= bitCnt + 1;
+      
       if( bitCnt == 7 ) begin
         byteCnt <= byteCnt +1;
+        transCnt <= transCnt + 1;
         rxBuf[byteCnt] <= exChangeReg;
         exChangeReg <= txBuf[byteCnt+1];
       end else begin
@@ -355,7 +360,7 @@ task spi_trans( input [15:0] saddress, input [7:0] scmd, input [12:0] slength,in
     txBuf[1] <= saddress[15:8];
     txBuf[2] <= scmd;
 
-    length <= slength;
+    length <= slength + 3;
     idx <= sidx;
 
     #5
@@ -364,8 +369,8 @@ task spi_trans( input [15:0] saddress, input [7:0] scmd, input [12:0] slength,in
     @(posedge sck) #5
     isReq <= 0;
 
-
-
+    @( negedge isBusy) #1000
+    begin end
   end
 
 endtask
@@ -420,6 +425,8 @@ initial begin
 
     txBuf[0+3] = 8'h01;
     spi_trans( (16'h20), (`SPI_WRITE), (1), (0) );//发送SM0 接收SM0, 请求发送
+    @(posedge isResp) #5 begin end
+
   end
 
 
@@ -471,7 +478,7 @@ initial begin
 
     txBuf[0+3] = 8'h01;
     spi_trans( (16'h20), (`SPI_WRITE), (1), (0) );//发送SM0 接收SM0, 请求发送
-
+    @(posedge isResp) #5 begin end
   end
 
 
@@ -575,7 +582,7 @@ initial begin
 
     txBuf[0+3] = 8'h01;
     spi_trans( (16'h20), (`SPI_WRITE), (1), (0) );//发送SM0 接收SM0, 请求发送
-
+    @(posedge isResp) #5 begin end
   end
 
 
@@ -646,7 +653,7 @@ initial begin
 
     txBuf[0+3] = 8'h01;
     spi_trans( (16'h20), (`SPI_WRITE), (1), (0) );//发送SM0 接收SM0, 请求发送
-
+    @(posedge isResp) #5 begin end
 
   end