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要求所有tx/rx时钟域异步复位

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RuigeLee
2023-09-25 14:18:27 +08:00
parent 5ff118f527
commit 51c39369c8
9 changed files with 45 additions and 43 deletions
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6
src/main/scala/mac/MacTilelink.scala
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@@ -88,7 +88,7 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod
val RxE_IRQ = Output(Bool())
val Busy_IRQ = Output(Bool())
val asyncReset = Input(AsyncReset())
}
@@ -1140,7 +1140,7 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod
trait MacTileLinkTXClk{ this: MacTileLinkBase =>
withClockAndReset( io.MTxClk.asClock, reset.asAsyncReset ) {
withClockAndReset( io.MTxClk.asClock, io.asyncReset ) {
val Flop = RegInit(false.B)
// Synchronizing BlockingTxStatusWrite to MTxClk
@@ -1313,7 +1313,7 @@ trait MacTileLinkTXClk{ this: MacTileLinkBase =>
trait MacTileLinkRXClk{ this: MacTileLinkBase =>
withClockAndReset( io.MRxClk.asClock, reset.asAsyncReset ){
withClockAndReset( io.MRxClk.asClock, io.asyncReset ){
val RxDataLatched2 = RegInit(0.U(32.W)); RxDataLatched2_rxclk := RxDataLatched2
val RxDataLatched1 = RegInit(0.U(24.W)) // Little Endian Byte Ordering[23:0]