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This commit is contained in:
RuigeLee
2025-09-05 17:15:04 +08:00
parent d5523eaa46
commit 4bc5e2927e
3 changed files with 25 additions and 23 deletions
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34
src/main/scala/backBoard/shin/Interface.scala
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@@ -52,9 +52,9 @@ class CommonRegisterBundle extends Bundle{
val refTop = UInt(3.W)
val bias = UInt(2.W)
val dwupEx = UInt(16.W)
val b8b4Sel = UInt(16.W)
val cdrParam = UInt(16.W)
val dwupEx = Bool()
val b8b4Sel = Bool()
val cdrParam = UInt(8.W)
val softResetCode = Vec(4, UInt(8.W))
@@ -308,9 +308,9 @@ abstract class InterfaceBase extends Module with RequireAsyncReset{
}) ++
Seq(
(addr === "h4a".U ) -> cReg.dwupEx.extract(0),
(addr === "h4c".U ) -> cReg.b8b4Sel.extract(0),
(addr === "h4e".U ) -> cReg.cdrParam(7,0),
(addr === "h4a".U ) -> cReg.dwupEx,
(addr === "h4c".U ) -> cReg.b8b4Sel,
(addr === "h4e".U ) -> cReg.cdrParam,
(addr === "h50".U ) -> cReg.anamuxSel,
(addr === "h51".U ) -> cReg.ldo2p5,
@@ -1071,22 +1071,14 @@ trait InterfaceSystem{ this: InterfaceBase =>
cReg.softResetCode(3) := RegEnable(dataw, 0.U(8.W), isEnW & addrw === "h43".U )
cReg.dwupEx :=
Cat(
RegEnable(dataw, 0.U(8.W), isEnW & addrw === "h4b".U ),
RegEnable(dataw, 0.U(8.W), isEnW & addrw === "h4a".U )
)
val dwupExTemp = RegEnable(dataw, 0.U(8.W), isEnW & addrw === "h4a".U )
cReg.dwupEx := RegEnable(dwupExTemp, 0.U(8.W), isEnW & addrw === "h4b".U & dataw === "h58".U )
cReg.b8b4Sel :=
Cat(
RegEnable(dataw, 0.U(8.W), isEnW & addrw === "h4d".U ),
RegEnable(dataw, 0.U(8.W), isEnW & addrw === "h4c".U )
)
cReg.cdrParam :=
Cat(
RegEnable(dataw, 0.U(8.W), isEnW & addrw === "h4f".U ),
RegEnable(dataw, 0.U(8.W), isEnW & addrw === "h4e".U )
)
val b8b4SelTemp = RegEnable(dataw, 0.U(8.W), isEnW & addrw === "h4c".U )
cReg.b8b4Sel := RegEnable(b8b4SelTemp, 0.U(8.W), isEnW & addrw === "h4d".U & dataw === "h59".U )
val cdrParamTemp = RegEnable(dataw, 0.U(8.W), isEnW & addrw === "h4e".U )
cReg.cdrParam := RegEnable(cdrParamTemp, 0.U(8.W), isEnW & addrw === "h4f".U & dataw === "h60".U )
val lvdsWriteAble = RegInit(0.U(16.W)); sReg.lvdsWriteAble := lvdsWriteAble
when( io.lvds.isEnW & (io.lvds.addrw === "h19".U(16.W)) ){