From 4bc5e2927e517dd16559067585dc53dac016bdd4 Mon Sep 17 00:00:00 2001
From: RuigeLee <wut.ruigeli@gmail.com>
Date: Fri, 5 Sep 2025 17:15:04 +0800
Subject: [PATCH] =?UTF-8?q?=E4=BF=AE=E6=94=B9key=E7=AD=96=E7=95=A5?=
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---
 src/main/scala/backBoard/shin/Interface.scala | 34 +++++++------------
 .../scala/backBoard/shin/MstSlvSwitch.scala   |  9 ++++-
 src/main/scala/backBoard/shin/ShinTop.scala   |  5 ++-
 3 files changed, 25 insertions(+), 23 deletions(-)

diff --git a/src/main/scala/backBoard/shin/Interface.scala b/src/main/scala/backBoard/shin/Interface.scala
index 782d85c..254c703 100644
--- a/src/main/scala/backBoard/shin/Interface.scala
+++ b/src/main/scala/backBoard/shin/Interface.scala
@@ -52,9 +52,9 @@ class CommonRegisterBundle extends Bundle{
   val refTop = UInt(3.W)
   val bias   = UInt(2.W)
 
-  val dwupEx   = UInt(16.W)
-  val b8b4Sel  = UInt(16.W)
-  val cdrParam = UInt(16.W)
+  val dwupEx   = Bool()
+  val b8b4Sel  = Bool()
+  val cdrParam = UInt(8.W)
 
 
   val softResetCode = Vec(4, UInt(8.W))
@@ -308,9 +308,9 @@ abstract class InterfaceBase extends Module with RequireAsyncReset{
       }) ++
 
       Seq(
-        (addr === "h4a".U ) -> cReg.dwupEx.extract(0),
-        (addr === "h4c".U ) -> cReg.b8b4Sel.extract(0),
-        (addr === "h4e".U ) -> cReg.cdrParam(7,0),
+        (addr === "h4a".U ) -> cReg.dwupEx,
+        (addr === "h4c".U ) -> cReg.b8b4Sel,
+        (addr === "h4e".U ) -> cReg.cdrParam,
 
         (addr === "h50".U ) -> cReg.anamuxSel,
         (addr === "h51".U ) -> cReg.ldo2p5,
@@ -1071,22 +1071,14 @@ trait InterfaceSystem{ this: InterfaceBase =>
   cReg.softResetCode(3) := RegEnable(dataw, 0.U(8.W), isEnW & addrw === "h43".U )
 
 
-  cReg.dwupEx   := 
-    Cat(
-      RegEnable(dataw, 0.U(8.W), isEnW & addrw === "h4b".U ),
-      RegEnable(dataw, 0.U(8.W), isEnW & addrw === "h4a".U )
-    )
+  val dwupExTemp = RegEnable(dataw, 0.U(8.W), isEnW & addrw === "h4a".U )
+  cReg.dwupEx   := RegEnable(dwupExTemp, 0.U(8.W), isEnW & addrw === "h4b".U & dataw === "h58".U )
 
-  cReg.b8b4Sel  := 
-    Cat(
-      RegEnable(dataw, 0.U(8.W), isEnW & addrw === "h4d".U ),
-      RegEnable(dataw, 0.U(8.W), isEnW & addrw === "h4c".U )
-    )
-  cReg.cdrParam := 
-    Cat(
-      RegEnable(dataw, 0.U(8.W), isEnW & addrw === "h4f".U ),
-      RegEnable(dataw, 0.U(8.W), isEnW & addrw === "h4e".U )
-    )
+  val b8b4SelTemp = RegEnable(dataw, 0.U(8.W), isEnW & addrw === "h4c".U )
+  cReg.b8b4Sel  := RegEnable(b8b4SelTemp, 0.U(8.W), isEnW & addrw === "h4d".U & dataw === "h59".U )
+
+  val cdrParamTemp = RegEnable(dataw, 0.U(8.W), isEnW & addrw === "h4e".U )
+  cReg.cdrParam := RegEnable(cdrParamTemp, 0.U(8.W), isEnW & addrw === "h4f".U & dataw === "h60".U )
 
   val lvdsWriteAble = RegInit(0.U(16.W)); sReg.lvdsWriteAble := lvdsWriteAble
   when( io.lvds.isEnW & (io.lvds.addrw === "h19".U(16.W)) ){
diff --git a/src/main/scala/backBoard/shin/MstSlvSwitch.scala b/src/main/scala/backBoard/shin/MstSlvSwitch.scala
index 881d5d1..9814eae 100644
--- a/src/main/scala/backBoard/shin/MstSlvSwitch.scala
+++ b/src/main/scala/backBoard/shin/MstSlvSwitch.scala
@@ -611,12 +611,19 @@ trait MstSlvSwitchB8B4{ this: MstSlvSwitchBase =>
   }
 }
 
+trait MstSlvSwitchCDRIn{ this: MstSlvSwitchBase =>
+  val cdrSelB = interface.io.cReg.cdrParam(15,8) === "h60".U && interface.io.cReg.b8b4Sel(7,0) === 1.U
+  val cdrSelC = interface.io.cReg.cdrParam(15,8) === "h60".U && interface.io.cReg.b8b4Sel(7,0) === 2.U
+  val cdrSelA = ~cdrSelB & ~cdrSelC
+}
+
 class MstSlvSwitch extends MstSlvSwitchBase
 with MstSlvSwitchMaster
 with MstSlvSwitchSlave
 with MstSlvSwitchWatchDog
 with MstSlvSwitchDataPath
-with MstSlvSwitchB8B4{
+with MstSlvSwitchB8B4
+with MstSlvSwitchCDRIn{
 
 
 
diff --git a/src/main/scala/backBoard/shin/ShinTop.scala b/src/main/scala/backBoard/shin/ShinTop.scala
index 9c634c5..db9567d 100644
--- a/src/main/scala/backBoard/shin/ShinTop.scala
+++ b/src/main/scala/backBoard/shin/ShinTop.scala
@@ -16,8 +16,9 @@ class ShinTop extends Module with RequireAsyncReset{
   val mstSlvSwitch = Module(new MstSlvSwitch)
   val downCDROut = Module(new CDROut)
   val upCDROut   = Module(new CDROut)
+
   val downCDRIn = Module(new MPCDRIn)
-  val upCDRIn   = Module(new MPCDRIn)
+  val upCDRIn  = Module(new MPCDRIn)
 
 
   downCDRIn.multiCLK := io.multiCLK
@@ -26,9 +27,11 @@ class ShinTop extends Module with RequireAsyncReset{
 
   downCDROut.io <> mstSlvSwitch.io.downCDROut
   upCDROut.io   <> mstSlvSwitch.io.upCDROut
+
   downCDRIn.io  <> mstSlvSwitch.io.downCDRIn
   upCDRIn.io    <> mstSlvSwitch.io.upCDRIn
 
+
   io.viewAsSupertype(new TopBase_IO_Bundle) <> mstSlvSwitch.io.viewAsSupertype(new TopBase_IO_Bundle)