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CDR拉到顶层

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This commit is contained in:
Ruige Lee
2025-08-26 17:52:23 +08:00
parent c6bd7902e7
commit 4b90a2c9bd
2 changed files with 78 additions and 101 deletions
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83
src/main/scala/backBoard/shin/ShinTop.scala
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@@ -3,94 +3,33 @@ package BACK
import chisel3._
import chisel3.util._
import chisel3.experimental.dataview._
class ShinTopIO extends Bundle{
val dDatIn = Input(Bool())
val dDatOut = Output(Bool())
val uDatIn = Input(Bool())
val uDatOut = Output(Bool())
class ShinTopIO extends TopBase_IO_Bundle{
val multiCLK = Input(Vec(16, Bool()))
val iqspi = new QSPIInterfaceIO
val ospi = new SSPIInterfaceIO
val oqspi = new QSPIInterfaceIO
val iSync = Output(Vec(4, Bool()))
val isSoftReset = Output(Bool())
val interrupt = Output(Bool())
val latchPin = Input(Vec(2, Bool()))
val hwSerial = Input(UInt(48.W))
val uniCode = Input(UInt(64.W))
val pllCtrl = Output(UInt(32.W))
val xtal = Output(UInt(12.W))
val anamuxSel = Output(UInt(5.W))
val ldo2p5 = Output(UInt(8.W))
val ldo1p1 = Output(UInt(8.W))
val refTop = Output(UInt(3.W))
val bias = Output(UInt(2.W))
val spiSel = Output(UInt(2.W))
}
class ShinTop extends Module with RequireAsyncReset{
val io: ShinTopIO = IO(new ShinTopIO)
downCDRIn.multiCLK := io.multiCLK
upCDRIn.multiCLK := io.multiCLK
val mstSlvSwitch = Module(new MstSlvSwitch)
val downCDROut = Module(new CDROut)
val upCDROut = Module(new CDROut)
val downCDRIn = Module(new MPCDRIn)
val upCDRIn = Module(new MPCDRIn)
downCDRIn.multiCLK := io.multiCLK
upCDRIn.multiCLK := io.multiCLK
downCDROut.io <> mstSlvSwitch.io.downCDROut
upCDROut.io <> mstSlvSwitch.io.upCDROut
downCDRIn.io <> mstSlvSwitch.io.downCDRIn
upCDRIn.io <> mstSlvSwitch.io.upCDRIn
when( interface.io.cReg.modeSel === false.B ){ //slave
when( (slaveParser.io.intHWTrig(0) | slaveParser.io.intHWTrig(1)) | interface.io.isPoReset ){ //硬件错误
downCDRIn.io.serDat := false.B
upCDRIn.io.serDat := false.B
when( slaveParser.io.isLoop ){ //回环
io.dDatOut := false.B
io.uDatOut := io.dDatIn
} .otherwise{ //非回环
io.dDatOut := io.dDatIn
io.uDatOut := io.uDatIn
}
} .otherwise{ //无硬件错误
when( slaveParser.io.isLoop ){ //回环
downCDRIn.io.serDat := io.dDatIn
upCDRIn.io.serDat := downCDROut.io.serDat
io.dDatOut := false.B
io.uDatOut := upCDROut.io.serDat
} .otherwise{ //非回环
downCDRIn.io.serDat := io.dDatIn
upCDRIn.io.serDat := io.uDatIn
io.dDatOut := downCDROut.io.serDat
io.uDatOut := upCDROut.io.serDat
}
}
} .otherwise{ //master
downCDRIn.io.serDat := false.B
upCDRIn.io.serDat := io.uDatIn
io.dDatOut := downCDROut.io.serDat
io.uDatOut := false.B
}
io.viewAsSupertype(new TopBase_IO_Bundle) <> mstSlvSwitch.io.viewAsSupertype(new TopBase_IO_Bundle)