From 4b90a2c9bd086d9702f284d72af21492547cdb52 Mon Sep 17 00:00:00 2001 From: Ruige Lee Date: Tue, 26 Aug 2025 17:52:23 +0800 Subject: [PATCH] =?UTF-8?q?CDR=E6=8B=89=E5=88=B0=E9=A1=B6=E5=B1=82?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .../scala/backBoard/shin/MstSlvSwitch.scala | 96 +++++++++++++------ src/main/scala/backBoard/shin/ShinTop.scala | 83 +++------------- 2 files changed, 78 insertions(+), 101 deletions(-) diff --git a/src/main/scala/backBoard/shin/MstSlvSwitch.scala b/src/main/scala/backBoard/shin/MstSlvSwitch.scala index 54041bf..8bdfac4 100644 --- a/src/main/scala/backBoard/shin/MstSlvSwitch.scala +++ b/src/main/scala/backBoard/shin/MstSlvSwitch.scala @@ -3,16 +3,12 @@ package BACK import chisel3._ import chisel3.util._ - -class MstSlvSwitchIO extends Bundle{ - +class TopBase_IO_Bundle extends Bundle{ val dDatIn = Input(Bool()) val dDatOut = Output(Bool()) val uDatIn = Input(Bool()) val uDatOut = Output(Bool()) - val multiCLK = Input(Vec(16, Bool())) - val iqspi = new QSPIInterfaceIO val ospi = new SSPIInterfaceIO val oqspi = new QSPIInterfaceIO @@ -40,6 +36,17 @@ class MstSlvSwitchIO extends Bundle{ +class MstSlvSwitchIO extends TopBase_IO_Bundle{ + + val downCDROut = Flipped(new CDROutIO) + val upCDROut = Flipped(new CDROutIO) + val downCDRIn = Flipped(new CDRInIO) + val upCDRIn = Flipped(new CDRInIO) + +} + + + @@ -61,10 +68,10 @@ abstract class MstSlvSwitchBase extends Module with RequireAsyncReset{ interface.io.uniCode := io.uniCode interface.io.hwSerial := io.hwSerial - interface.io.intTransEnd(0) := downCDRIn.io.axis.fire & downCDRIn.io.axis.bits.tlast - interface.io.intTransEnd(1) := downCDROut.io.axis.fire & downCDROut.io.axis.bits.tlast - interface.io.intTransEnd(2) := upCDRIn.io.axis.fire & upCDRIn.io.axis.bits.tlast - interface.io.intTransEnd(3) := upCDROut.io.axis.fire & upCDROut.io.axis.bits.tlast + interface.io.intTransEnd(0) := io.downCDRIn.axis.fire & io.downCDRIn.axis.bits.tlast + interface.io.intTransEnd(1) := io.downCDROut.axis.fire & io.downCDROut.axis.bits.tlast + interface.io.intTransEnd(2) := io.upCDRIn.axis.fire & io.upCDRIn.axis.bits.tlast + interface.io.intTransEnd(3) := io.upCDROut.axis.fire & io.upCDROut.axis.bits.tlast io.isSoftReset := interface.io.isSoftReset io.interrupt := interface.io.interrupt @@ -203,24 +210,24 @@ abstract class MstSlvSwitchBase extends Module with RequireAsyncReset{ slaveParser.io.sram_r(3).datar := 0.U masterParser.io.sram_r.datar := 0.U - downCDRIn.io.axis.ready := false.B + io.downCDRIn.axis.ready := false.B slaveParser.io.downIn.valid := false.B slaveParser.io.downIn.bits := 0.U.asTypeOf(new AXIS_Bundle(8)) slaveParser.io.downOut.ready := false.B masterParser.io.downOut.ready := false.B - downCDROut.io.axis.valid := false.B - downCDROut.io.axis.bits := 0.U.asTypeOf(new AXIS_Bundle(8)) + io.downCDROut.axis.valid := false.B + io.downCDROut.axis.bits := 0.U.asTypeOf(new AXIS_Bundle(8)) - upCDRIn.io.axis.ready := false.B + io.upCDRIn.axis.ready := false.B slaveParser.io.upIn.valid := false.B slaveParser.io.upIn.bits := 0.U.asTypeOf(new AXIS_Bundle(8)) masterParser.io.upIn.valid := false.B masterParser.io.upIn.bits := 0.U.asTypeOf(new AXIS_Bundle(8)) slaveParser.io.upOut.ready := false.B - upCDROut.io.axis.valid := false.B - upCDROut.io.axis.bits := 0.U.asTypeOf(new AXIS_Bundle(8)) + io.upCDROut.axis.valid := false.B + io.upCDROut.axis.bits := 0.U.asTypeOf(new AXIS_Bundle(8)) interface.io.mstDeltaTime := 0.U @@ -252,8 +259,8 @@ abstract class MstSlvSwitchBase extends Module with RequireAsyncReset{ trait MstSlvSwitchMaster{ this: MstSlvSwitchBase => when( interface.io.cReg.modeSel === true.B ){ - masterParser.io.downOut <> downCDROut.io.axis - masterParser.io.upIn <> upCDRIn.io.axis + masterParser.io.downOut <> io.downCDROut.axis + masterParser.io.upIn <> io.upCDRIn.axis } when( interface.io.cReg.modeSel === true.B ){ @@ -312,10 +319,10 @@ trait MstSlvSwitchMaster{ this: MstSlvSwitchBase => trait MstSlvSwitchSlave{ this: MstSlvSwitchBase => when( interface.io.cReg.modeSel === false.B ){ - slaveParser.io.downIn <> downCDRIn.io.axis - downCDROut.io.axis <> slaveParser.io.downOut - slaveParser.io.upIn <> upCDRIn.io.axis - upCDROut.io.axis <> slaveParser.io.upOut + slaveParser.io.downIn <> io.downCDRIn.axis + io.downCDROut.axis <> slaveParser.io.downOut + slaveParser.io.upIn <> io.upCDRIn.axis + io.upCDROut.axis <> slaveParser.io.upOut } slaveParser.io.cReg := interface.io.cReg @@ -366,10 +373,10 @@ trait MstSlvSwitchSlave{ this: MstSlvSwitchBase => slaveParser.io.intHWClr(0) := interface.io.intHWTrig(0) & interface.io.intHWClr(0) slaveParser.io.intHWClr(1) := interface.io.intHWTrig(1) & interface.io.intHWClr(1) - downCDRIn.io.flush := RegNext( interface.io.intHWTrig(0) & interface.io.intHWClr(0) ) - upCDRIn.io.flush := RegNext( interface.io.intHWTrig(1) & interface.io.intHWClr(1) ) - downCDROut.io.flush := RegNext( interface.io.intHWTrig(0) & interface.io.intHWClr(0) ) - upCDROut.io.flush := RegNext( interface.io.intHWTrig(1) & interface.io.intHWClr(1) ) + io.downCDRIn.flush := RegNext( interface.io.intHWTrig(0) & interface.io.intHWClr(0) ) + io.upCDRIn.flush := RegNext( interface.io.intHWTrig(1) & interface.io.intHWClr(1) ) + io.downCDROut.flush := RegNext( interface.io.intHWTrig(0) & interface.io.intHWClr(0) ) + io.upCDROut.flush := RegNext( interface.io.intHWTrig(1) & interface.io.intHWClr(1) ) interface.io.lvds <> slaveParser.io.lvds @@ -385,7 +392,7 @@ trait MstSlvSwitchSlave{ this: MstSlvSwitchBase => } -trait MstSlvSwitchDog{ this: MstSlvSwitchBase => +trait MstSlvSwitchWatchDog{ this: MstSlvSwitchBase => //看门狗1~16，SM监控 val isWdtSMEnable = for( _ <- 0 until 16 ) yield { RegInit(false.B) } @@ -422,11 +429,11 @@ trait MstSlvSwitchDog{ this: MstSlvSwitchBase => val wdtRec2RtnCnt = Reg(UInt(32.W)) when( - (upCDRIn.io.axis.fire & upCDRIn.io.axis.bits.tlast) | + (io.upCDRIn.axis.fire & io.upCDRIn.axis.bits.tlast) | ~interface.io.cReg.wdtEnable.extract(0) ){ isWdtRec2RtnEnable := false.B - } .elsewhen( ~isWdtRec2RtnEnable & downCDROut.io.axis.fire & interface.io.cReg.wdtEnable.extract(0) ){ + } .elsewhen( ~isWdtRec2RtnEnable & io.downCDROut.axis.fire & interface.io.cReg.wdtEnable.extract(0) ){ isWdtRec2RtnEnable := true.B } @@ -447,7 +454,7 @@ trait MstSlvSwitchDog{ this: MstSlvSwitchBase => wdtRec2RecCnt := wdtRec2RecCnt + 1.U } .elsewhen( ~interface.io.cReg.wdtEnable.extract(17) || - downCDRIn.io.axis.fire || + io.downCDRIn.axis.fire || (wdtRec2RecCnt >= interface.io.cReg.wdtTarCnt(17)) ){ wdtRec2RecCnt := 0.U @@ -466,6 +473,37 @@ with MstSlvSwitchWatchDog{ + when( interface.io.cReg.modeSel === false.B ){ //slave + when( (slaveParser.io.intHWTrig(0) | slaveParser.io.intHWTrig(1)) | interface.io.isPoReset ){ //硬件错误 + io.downCDRIn.serDat := false.B + io.upCDRIn.serDat := false.B + when( slaveParser.io.isLoop ){ //回环 + io.dDatOut := false.B + io.uDatOut := io.dDatIn + } .otherwise{ //非回环 + io.dDatOut := io.dDatIn + io.uDatOut := io.uDatIn + } + } .otherwise{ //无硬件错误 + when( slaveParser.io.isLoop ){ //回环 + io.downCDRIn.serDat := io.dDatIn + io.upCDRIn.serDat := io.downCDROut.serDat + io.dDatOut := false.B + io.uDatOut := io.upCDROut.serDat + } .otherwise{ //非回环 + io.downCDRIn.serDat := io.dDatIn + io.upCDRIn.serDat := io.uDatIn + io.dDatOut := io.downCDROut.serDat + io.uDatOut := io.upCDROut.serDat + } + } + } .otherwise{ //master + io.downCDRIn.serDat := false.B + io.upCDRIn.serDat := io.uDatIn + io.dDatOut := io.downCDROut.serDat + io.uDatOut := false.B + } + diff --git a/src/main/scala/backBoard/shin/ShinTop.scala b/src/main/scala/backBoard/shin/ShinTop.scala index e9b548f..9c634c5 100644 --- a/src/main/scala/backBoard/shin/ShinTop.scala +++ b/src/main/scala/backBoard/shin/ShinTop.scala @@ -3,94 +3,33 @@ package BACK import chisel3._ import chisel3.util._ +import chisel3.experimental.dataview._ - -class ShinTopIO extends Bundle{ - - val dDatIn = Input(Bool()) - val dDatOut = Output(Bool()) - val uDatIn = Input(Bool()) - val uDatOut = Output(Bool()) - +class ShinTopIO extends TopBase_IO_Bundle{ val multiCLK = Input(Vec(16, Bool())) - - val iqspi = new QSPIInterfaceIO - val ospi = new SSPIInterfaceIO - val oqspi = new QSPIInterfaceIO - - val iSync = Output(Vec(4, Bool())) - - val isSoftReset = Output(Bool()) - - val interrupt = Output(Bool()) - - val latchPin = Input(Vec(2, Bool())) - val hwSerial = Input(UInt(48.W)) - val uniCode = Input(UInt(64.W)) - - val pllCtrl = Output(UInt(32.W)) - val xtal = Output(UInt(12.W)) - val anamuxSel = Output(UInt(5.W)) - val ldo2p5 = Output(UInt(8.W)) - val ldo1p1 = Output(UInt(8.W)) - val refTop = Output(UInt(3.W)) - val bias = Output(UInt(2.W)) - - val spiSel = Output(UInt(2.W)) } class ShinTop extends Module with RequireAsyncReset{ + val io: ShinTopIO = IO(new ShinTopIO) - - - downCDRIn.multiCLK := io.multiCLK - upCDRIn.multiCLK := io.multiCLK - - + val mstSlvSwitch = Module(new MstSlvSwitch) val downCDROut = Module(new CDROut) val upCDROut = Module(new CDROut) val downCDRIn = Module(new MPCDRIn) val upCDRIn = Module(new MPCDRIn) + downCDRIn.multiCLK := io.multiCLK + upCDRIn.multiCLK := io.multiCLK + downCDROut.io <> mstSlvSwitch.io.downCDROut + upCDROut.io <> mstSlvSwitch.io.upCDROut + downCDRIn.io <> mstSlvSwitch.io.downCDRIn + upCDRIn.io <> mstSlvSwitch.io.upCDRIn - - when( interface.io.cReg.modeSel === false.B ){ //slave - when( (slaveParser.io.intHWTrig(0) | slaveParser.io.intHWTrig(1)) | interface.io.isPoReset ){ //硬件错误 - downCDRIn.io.serDat := false.B - upCDRIn.io.serDat := false.B - when( slaveParser.io.isLoop ){ //回环 - io.dDatOut := false.B - io.uDatOut := io.dDatIn - } .otherwise{ //非回环 - io.dDatOut := io.dDatIn - io.uDatOut := io.uDatIn - } - } .otherwise{ //无硬件错误 - when( slaveParser.io.isLoop ){ //回环 - downCDRIn.io.serDat := io.dDatIn - upCDRIn.io.serDat := downCDROut.io.serDat - io.dDatOut := false.B - io.uDatOut := upCDROut.io.serDat - } .otherwise{ //非回环 - downCDRIn.io.serDat := io.dDatIn - upCDRIn.io.serDat := io.uDatIn - io.dDatOut := downCDROut.io.serDat - io.uDatOut := upCDROut.io.serDat - } - } - } .otherwise{ //master - downCDRIn.io.serDat := false.B - upCDRIn.io.serDat := io.uDatIn - io.dDatOut := downCDROut.io.serDat - io.uDatOut := false.B - } - - - + io.viewAsSupertype(new TopBase_IO_Bundle) <> mstSlvSwitch.io.viewAsSupertype(new TopBase_IO_Bundle)