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This commit is contained in:
Ruige Lee
2025-08-28 15:51:17 +08:00
parent 9bb59c350a
commit 4b88e4937d
3 changed files with 55 additions and 33 deletions
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2
src/main/scala/backBoard/shin/NSpiInterface.scala → src/main/scala/backBoard/shin/NSpiInterface.scala.bk
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@@ -107,7 +107,7 @@ class SyncSSpiInterface extends SyncSpiInterfaceBase{
dataw_async dataw_async
isEnR_async := bitSel === 1.U & (byteSel >= 2.U) & isSpiRead // isEnR_async := bitSel === 1.U & (byteSel >= 2.U) & isSpiRead
// isEnW_async := bitSel === 0.U & (byteSel >= 4.U) & isSpiWrite // isEnW_async := bitSel === 0.U & (byteSel >= 4.U) & isSpiWrite
val isEnWSet_async = withClockAndReset(spi.sck.asClock, spi.csn){ RegInit(false.B) } val isEnWSet_async = withClockAndReset(spi.sck.asClock, spi.csn){ RegInit(false.B) }

76
src/main/scala/backBoard/shin/SpiInterface.scala
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@@ -59,7 +59,9 @@ abstract class SpiInterfaceBase extends Module with RequireAsyncReset{
val isSpiRead = spiCmd === 1.U val isSpiRead = spiCmd === 1.U
val bitSel = Reg(UInt(3.W)) val bitSel = Reg(UInt(3.W))
val bitSelNext = RegNext(bitSel)
val byteSel = Reg(UInt(12.W)) val byteSel = Reg(UInt(12.W))
val byteSelNext = RegNext(byteSel)
@@ -95,17 +97,7 @@ abstract class SpiInterfaceBase extends Module with RequireAsyncReset{
} }
} }
when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳
addrr := 0.U
} .elsewhen(isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel === 0.U & byteSel === 1.U){ //CS为低，且SCK上跳的第0byte
addrr := exRegi
} .elsewhen(isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel === 0.U & byteSel === 2.U) {//CS为低，且SCK上跳的第0byte
addrr := Cat(addrr(7,0), exRegi)
} .otherwise{ // byteSel > 1.U
when( isSckPosedgeNext(1) & byteSel > 3.U & bitSel === 0.U ){
addrr := addrr + 1.U
}
}
@@ -116,16 +108,17 @@ abstract class SpiInterfaceBase extends Module with RequireAsyncReset{
class SSpiInterface extends SpiInterfaceBase{ class SSpiInterface extends SpiInterfaceBase{
val spi = IO(new SSPIInterfaceIO) val spi = IO(new SSPIInterfaceIO)
val shiftMOSI = ShiftRegisters(spi.mosi, 3)
sck := spi.sck sck := spi.sck
csn := spi.csn csn := spi.csn
io.isEnR := io.isEnR :=
(isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel === 0.U & spi.miso === 1.U & byteSel === 2.U ) | (isSckPosedgeNext(0) & ~shiftCSn(1) & bitSelNext === 0.U & shiftMOSI(1) === 1.U & byteSelNext === 2.U ) |
(isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel === 0.U & isSpiRead & byteSel >= 3.U) (isSckPosedgeNext(0) & ~shiftCSn(1) & bitSelNext === 0.U & isSpiRead & byteSelNext >= 3.U)
when( isSckPosedgeNext(0) & ~shiftCSn(1) & byteSel === 2.U & bitSel === 0.U ){ //CS为低，且SCK上跳的第0byte when( isSckPosedgeNext(0) & ~shiftCSn(1) & byteSelNext === 2.U & bitSelNext === 0.U ){ //CS为低，且SCK上跳的第0byte
spiCmd := spi.miso spiCmd := shiftMOSI(1)
} }
@@ -137,7 +130,7 @@ class SSpiInterface extends SpiInterfaceBase{
bitSel := bitSel + 1.U bitSel := bitSel + 1.U
} }
val shiftMOSI = ShiftRegisters(spi.mosi, 3)
//输入看SCK上升沿 //输入看SCK上升沿
when( isSckPosedge & ~shiftCSn(1) ){ when( isSckPosedge & ~shiftCSn(1) ){
@@ -151,9 +144,9 @@ class SSpiInterface extends SpiInterfaceBase{
//输出在SCK下降沿准备数据 //输出在SCK下降沿准备数据
when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳 when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳
exRego := 0.U //第一个byte 地址0 exRego := 0.U //第一个byte 地址0
} .elsewhen( isSckNegedge & ~shiftCSn(1) ){ } .elsewhen( isSckPosedge & ~shiftCSn(1) ){
when( bitSel === 0.U ){ when( bitSel.andR ){
when((byteSel === 1.U || byteSel === 2.U) ){ when((byteSel === 0.U || byteSel === 1.U) ){
exRego := 0.U //地址1，cmd exRego := 0.U //地址1，cmd
} .elsewhen( isSpiRead ){ } .elsewhen( isSpiRead ){
exRego := io.datar exRego := io.datar
@@ -162,10 +155,26 @@ class SSpiInterface extends SpiInterfaceBase{
exRego := exRego << 1 exRego := exRego << 1
} }
} }
when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳
addrr := 0.U
} .elsewhen(isSckPosedge & ~shiftCSn(1) & bitSel.andR & byteSel === 0.U){ //CS为低，且SCK上跳的第0byte
addrr := Cat( exRegi(6,0), shiftMOSI(1) )
} .elsewhen(isSckPosedge & ~shiftCSn(1) & bitSel.andR & byteSel === 1.U) {//CS为低，且SCK上跳的第0byte
addrr := Cat(addrr(7,0), exRegi(6,0), shiftMOSI(1))
} .otherwise{ // byteSel > 1.U
when( isSckPosedgeNext(0) & byteSelNext >= 2.U & bitSelNext === 0.U ){
addrr := addrr + 1.U
}
}
} }
class QSpiInterface extends SpiInterfaceBase{ class QSpiInterface extends SpiInterfaceBase{
val qspi = IO(new QSPIInterfaceIO) val qspi = IO(new QSPIInterfaceIO)
val shiftMOSI = ShiftRegisters(qspi.mosi, 3)
sck := qspi.sck sck := qspi.sck
csn := qspi.csn csn := qspi.csn
@@ -173,11 +182,11 @@ class QSpiInterface extends SpiInterfaceBase{
qspi.isDirIn := ~isSpiRead qspi.isDirIn := ~isSpiRead
io.isEnR := io.isEnR :=
(isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel === 0.U & qspi.miso === "b1000".U & byteSel === 2.U ) | (isSckPosedgeNext(0) & ~shiftCSn(1) & bitSelNext === 0.U & shiftMOSI(1) === "b1000".U & byteSelNext === 2.U ) |
(isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel === 0.U & isSpiRead & byteSel >= 3.U) (isSckPosedgeNext(0) & ~shiftCSn(1) & bitSelNext === 0.U & isSpiRead & byteSelNext >= 3.U)
when( isSckPosedgeNext(0) & ~shiftCSn(1) & byteSel === 2.U & bitSel === 0.U ){ //CS为低，且SCK上跳的第0byte when( isSckPosedgeNext(0) & ~shiftCSn(1) & byteSelNext === 2.U & bitSelNext === 0.U ){ //CS为低，且SCK上跳的第0byte
spiCmd := qspi.miso.extract(3) spiCmd := shiftMOSI(1).extract(3)
} }
when( shiftCSn(2) & ~shiftCSn(1) ){ when( shiftCSn(2) & ~shiftCSn(1) ){
@@ -186,7 +195,7 @@ class QSpiInterface extends SpiInterfaceBase{
bitSel := ~bitSel bitSel := ~bitSel
} }
val shiftMOSI = ShiftRegisters(qspi.mosi, 3)
@@ -202,9 +211,9 @@ class QSpiInterface extends SpiInterfaceBase{
//输出在SCK下降沿准备数据 //输出在SCK下降沿准备数据
when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳 when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳
exRego := 0.U //第一个byte 地址0 exRego := 0.U //第一个byte 地址0
} .elsewhen( isSckNegedge & ~shiftCSn(1) ){ } .elsewhen( isSckPosedge & ~shiftCSn(1) ){
when( bitSel === 0.U ){ when( bitSel.andR ){
when((byteSel === 1.U || byteSel === 2.U) ){ when((byteSel === 0.U || byteSel === 1.U) ){
exRego := 0.U //地址1，cmd exRego := 0.U //地址1，cmd
} .elsewhen( isSpiRead ){ } .elsewhen( isSpiRead ){
exRego := io.datar exRego := io.datar
@@ -214,6 +223,19 @@ class QSpiInterface extends SpiInterfaceBase{
} }
} }
when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳
addrr := 0.U
} .elsewhen(isSckPosedge & ~shiftCSn(1) & bitSel.andR & byteSel === 0.U){ //CS为低，且SCK上跳的第0byte
addrr := Cat( exRegi(3,0), shiftMOSI(1) )
} .elsewhen(isSckPosedge & ~shiftCSn(1) & bitSel.andR & byteSel === 1.U) {//CS为低，且SCK上跳的第0byte
addrr := Cat(addrr(7,0), exRegi(3,0), shiftMOSI(1))
} .otherwise{ // byteSel > 1.U
when( isSckPosedgeNext(0) & byteSelNext >= 2.U & bitSelNext === 0.U ){
addrr := addrr + 1.U
}
}
} }

6
tb/shinTest/ShinTopSpiTb.v
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@@ -552,11 +552,11 @@ always @(posedge sck) begin
if( &bitCnt ) begin if( &bitCnt ) begin
byteCnt <= byteCnt +1; byteCnt <= byteCnt +1;
transCnt <= transCnt + 1; transCnt <= transCnt + 1;
if( txBuf[2] === 1 & nextByteCnt >= 4) begin if( txBuf[2] === 8'h80 & nextByteCnt >= 4) begin
rxBuf[byteCnt] <= exChangeRegi; rxBuf[byteCnt] <= exChangeRegi;
//$display("spi read out %x", exChangeRegi); //$display("spi read out %x", exChangeRegi);
end end
if( txBuf[2] === 1 & nextByteCnt >= 3) begin if( txBuf[2] === 8'h80 & nextByteCnt >= 3) begin
exChangeRegi <= isQspi ? {exChangeRegi[3:0], qspi_mux_miso} : {exChangeRegi[6:0], spi_mux_miso}; exChangeRegi <= isQspi ? {exChangeRegi[3:0], qspi_mux_miso} : {exChangeRegi[6:0], spi_mux_miso};
end else begin end else begin
exChangeRegi <= 0; exChangeRegi <= 0;
@@ -775,7 +775,7 @@ end
`define IF_OQSPI(idx) ((`ALL_DEV_NUM * 2) + (idx)) `define IF_OQSPI(idx) ((`ALL_DEV_NUM * 2) + (idx))
`define IF_OSPI(idx) ((`ALL_DEV_NUM) + (idx)) `define IF_OSPI(idx) ((`ALL_DEV_NUM) + (idx))
`define SPI_WRITE 8'h0 `define SPI_WRITE 8'h0
`define SPI_READ 8'h1 `define SPI_READ 8'h80
`define MST_TX_TRIGGER(idx) (8'h1 + ((idx & 8'h3) * 8'h2) + ((idx & 8'h3) * 8'h8)) `define MST_TX_TRIGGER(idx) (8'h1 + ((idx & 8'h3) * 8'h2) + ((idx & 8'h3) * 8'h8))
`define MST_RX0_ADDR 16'h0800 `define MST_RX0_ADDR 16'h0800