148 lines
3.9 KiB
Plaintext
148 lines
3.9 KiB
Plaintext
package BACK
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import chisel3._
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import chisel3.util._
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abstract class SyncSpiInterfaceBase extends Module with RequireAsyncReset{
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val io = IO(new RegAccessInterfaceIO)
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}
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class SyncSSpiInterface extends SyncSpiInterfaceBase{
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val spi = IO(new SSPIInterfaceIO)
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// withClockAndReset(sck.asClock, reset.asBool){
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spi.miso := exRego.extract(7)
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val bitSel = withClockAndReset(spi.sck.asClock, spi.csn){RegInit(0.U(3.W)) }
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val byteSel = withClockAndReset(spi.sck.asClock, spi.csn){RegInit(0.U(12.W))}
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val exRego = withClockAndReset(spi.sck.asClock, spi.csn){RegInit(0.U(8.W))}
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val exRegi = withClockAndReset(spi.sck.asClock, spi.csn){RegInit(0.U(8.W))}
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when( true.B ){
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bitSel := bitSel + 1.U
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}
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when( bitSel.andR ){
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byteSel := byteSel + 1.U
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}
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when( true.B ){
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exRegi := Cat( exRegi(6 ,0), spi.mosi )
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}
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when( bitSel === 0.U ){
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when((byteSel === 1.U || byteSel === 2.U) ){
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exRego := 0.U //地址1，cmd
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} .elsewhen( isSpiRead ){
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exRego := datar_async
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}
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}.otherwise{
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exRego := exRego << 1
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}
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val addrw_async = withClockAndReset(spi.sck.asClock, spi.csn){ RegInit(0.U(16.W)) }
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val addrr_async = withClockAndReset(spi.sck.asClock, spi.csn){ RegInit(0.U(16.W)) }
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val dataw_async = withClockAndReset(spi.sck.asClock, spi.csn){ RegInit(0.U(8.W)) }
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val datar_async = withClockAndReset(spi.sck.asClock, spi.csn){ RegInit(0.U(8.W)) }
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val spiCmd = withClockAndReset(spi.sck.asClock, spi.csn){ RegInit(false.B) }
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val isSpiWrite = ~spiCmd
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val isSpiRead = spiCmd
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when( bitSel === 0.U ){
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when( byteSel === 1.U ){
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addrw_async := exRegi
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} .elsewhen( byteSel === 2.U ) {
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addrw_async := Cat(addrw_async(7,0), exRegi)
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} .elsewhen( byteSel > 3.U ){
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addrw_async := addrw_async + 1.U
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}
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}
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when( bitSel === 0.U ){
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when( byteSel === 1.U ){
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addrr_async := exRegi
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} .elsewhen( byteSel === 2.U ) {
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addrr_async := Cat(addrr_async(7,0), exRegi)
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} .elsewhen( byteSel > 2.U ){
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addrr_async := addrr_async + 1.U
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}
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}
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when( byteSel === 2.U & bitSel === 0.U ){ //CS为低，且SCK上跳的第0byte
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spiCmd := spi.mosi
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}
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when( bitSel === 0.U ){
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when( byteSel > 3.U & isSpiWrite ){
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dataw_async := exRegi
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}
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}
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io.dataw := exRegi
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io.addrr := Mux( isSpiRead, addrr + 1.U, addrr )
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// io.addrSel :=
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// Mux( isSpiRead, addrSel + 1.U, addrSel )//覆盖三种情况
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// val readData = RegEnable(io.datar, io.isEnR)
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isEnW_async
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isEnR_async
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addrw_async
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addrr_async
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datar_async
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dataw_async
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// isEnR_async := bitSel === 1.U & (byteSel >= 2.U) & isSpiRead
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// isEnW_async := bitSel === 0.U & (byteSel >= 4.U) & isSpiWrite
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val isEnWSet_async = withClockAndReset(spi.sck.asClock, spi.csn){ RegInit(false.B) }
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val isEnWSet_sync = ShiftRegisters(isEnWSet_async, 3, false.B, true.B)
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val isEnWReset_async = withClockAndReset(spi.sck.asClock, spi.csn){ ShiftRegister(isEnWSet_sync(1), 2, false.B, true.B) }
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when( bitSel === 0.U & (byteSel >= 4.U) & isSpiWrite ){
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assert( ~isEnWSet_async, "Assert Failed @spi!\n" )
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isEnWSet_async := true.B
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} .elsewhen(isEnWReSet_async){
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isEnWSet_async := false.B
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}
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io.isEnW := ~isEnWSet_async(2) & isEnWSet_async(1)
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io.addrw := addrw_async
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io.dataw := dataw_async
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val isEnRSet_async = withClockAndReset(spi.sck.asClock, spi.csn){ RegInit(false.B) }
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val isEnRSet_sync = ShiftRegisters(isEnRSet_async, 3, false.B, true.B)
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val isEnRReset_async = withClockAndReset(spi.sck.asClock, spi.csn){ ShiftRegister(isEnRSet_sync(1), 2, false.B, true.B) }
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when( bitSel === 1.U & (byteSel >= 2.U) & isSpiRead ){
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assert( ~isEnRSet_async, "Assert Failed @spi!\n" )
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isEnRSet_async := true.B
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} .elsewhen(isEnRReSet_async){
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isEnRSet_async := false.B
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}
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io.isEnR := ~isEnRSet_async(2) & isEnRSet_async(1)
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io.addrr := addrr_async
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datar_async := withClockAndReset(spi.sck.asClock, spi.csn){ RegEnable(io.datar, 0.U, isEnRReSet_async }
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}
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