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lvds读方向负负得正修复

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Ruige Lee
2025-05-23 10:43:44 +08:00
parent 1b836f9805
commit 4b5f45e342
1 changed files with 4 additions and 4 deletions
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8
src/main/scala/backBoard/shin/SlaveParser.scala
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@@ -570,13 +570,13 @@ trait SlaveParserRW{ this: SlaveParserBase =>
io.dSMenq(0) := io.sram_w(0).enw & isWRSM0 & (io.cReg.smTrigLen(0) - 1.U) === addrw(10,0)
io.uSMdeq(0) := isLvdsEnR & isRDSM1 & (io.cReg.smTrigLen(1) - 1.U) === addrr(10,0)
io.uSMdeq(0) := isLvdsEnR & isRDSM1 & (io.cReg.smTrigLen(1) - 1.U + 1.U) === addrr(10,0)
io.dSMenq(1) := io.sram_w(1).enw & isWRSM2 & (io.cReg.smTrigLen(2) - 1.U) === addrw(10,0)
io.uSMdeq(1) := isLvdsEnR & isRDSM3 & (io.cReg.smTrigLen(3) - 1.U) === addrr(10,0)
io.uSMdeq(1) := isLvdsEnR & isRDSM3 & (io.cReg.smTrigLen(3) - 1.U + 1.U) === addrr(10,0)
io.dSMenq(2) := io.sram_w(2).enw & isWRSM4 & (io.cReg.smTrigLen(4) - 1.U) === addrw(10,0)
io.uSMdeq(2) := isLvdsEnR & isRDSM5 & (io.cReg.smTrigLen(5) - 1.U) === addrr(10,0)
io.uSMdeq(2) := isLvdsEnR & isRDSM5 & (io.cReg.smTrigLen(5) - 1.U + 1.U) === addrr(10,0)
io.dSMenq(3) := io.sram_w(3).enw & isWRSM6 & (io.cReg.smTrigLen(6) - 1.U) === addrw(10,0)
io.uSMdeq(3) := isLvdsEnR & isRDSM7 & (io.cReg.smTrigLen(7) - 1.U) === addrr(10,0)
io.uSMdeq(3) := isLvdsEnR & isRDSM7 & (io.cReg.smTrigLen(7) - 1.U + 1.U) === addrr(10,0)
}