From 4b5f45e342e384541b34876fce56b88b86431d2f Mon Sep 17 00:00:00 2001 From: Ruige Lee Date: Fri, 23 May 2025 10:43:44 +0800 Subject: [PATCH] =?UTF-8?q?lvds=E8=AF=BB=E6=96=B9=E5=90=91=E8=B4=9F?= =?UTF-8?q?=E8=B4=9F=E5=BE=97=E6=AD=A3=E4=BF=AE=E5=A4=8D?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/shin/SlaveParser.scala | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/main/scala/backBoard/shin/SlaveParser.scala b/src/main/scala/backBoard/shin/SlaveParser.scala index 3e059d8..ef91ef9 100644 --- a/src/main/scala/backBoard/shin/SlaveParser.scala +++ b/src/main/scala/backBoard/shin/SlaveParser.scala @@ -570,13 +570,13 @@ trait SlaveParserRW{ this: SlaveParserBase => io.dSMenq(0) := io.sram_w(0).enw & isWRSM0 & (io.cReg.smTrigLen(0) - 1.U) === addrw(10,0) - io.uSMdeq(0) := isLvdsEnR & isRDSM1 & (io.cReg.smTrigLen(1) - 1.U) === addrr(10,0) + io.uSMdeq(0) := isLvdsEnR & isRDSM1 & (io.cReg.smTrigLen(1) - 1.U + 1.U) === addrr(10,0) io.dSMenq(1) := io.sram_w(1).enw & isWRSM2 & (io.cReg.smTrigLen(2) - 1.U) === addrw(10,0) - io.uSMdeq(1) := isLvdsEnR & isRDSM3 & (io.cReg.smTrigLen(3) - 1.U) === addrr(10,0) + io.uSMdeq(1) := isLvdsEnR & isRDSM3 & (io.cReg.smTrigLen(3) - 1.U + 1.U) === addrr(10,0) io.dSMenq(2) := io.sram_w(2).enw & isWRSM4 & (io.cReg.smTrigLen(4) - 1.U) === addrw(10,0) - io.uSMdeq(2) := isLvdsEnR & isRDSM5 & (io.cReg.smTrigLen(5) - 1.U) === addrr(10,0) + io.uSMdeq(2) := isLvdsEnR & isRDSM5 & (io.cReg.smTrigLen(5) - 1.U + 1.U) === addrr(10,0) io.dSMenq(3) := io.sram_w(3).enw & isWRSM6 & (io.cReg.smTrigLen(6) - 1.U) === addrw(10,0) - io.uSMdeq(3) := isLvdsEnR & isRDSM7 & (io.cReg.smTrigLen(7) - 1.U) === addrr(10,0) + io.uSMdeq(3) := isLvdsEnR & isRDSM7 & (io.cReg.smTrigLen(7) - 1.U + 1.U) === addrr(10,0) }