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卡总线 发送正确

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This commit is contained in:
RuigeLee
2024-10-30 10:24:22 +08:00
parent 9058337ffe
commit 498fa92a80
3 changed files with 21 additions and 23 deletions
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26
src/main/scala/backBoard/pico/TLCDR.scala
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@@ -18,7 +18,7 @@ abstract class TLCDRBase(val edge: TLEdgeIn)(implicit p: Parameters) extends Bac
val tla = Flipped(new DecoupledIO(new TLBundleA(edge.bundle))) val tla = Flipped(new DecoupledIO(new TLBundleA(edge.bundle)))
val tld = new DecoupledIO(new TLBundleD(edge.bundle)) val tld = new DecoupledIO(new TLBundleD(edge.bundle))
val interrupt = Output(Vec(5, Bool())) val interrupt = Output(Vec(4, Bool()))
} }
val io: TLCDRIO = IO(new TLCDRIO) val io: TLCDRIO = IO(new TLCDRIO)
@@ -127,14 +127,24 @@ trait TLCDRRx{ this: TLCDRBase =>
// val isRxBusy = RegInit(false.B) // val isRxBusy = RegInit(false.B)
val isRxValid = rxFifo.io.enq.fire val isRxValid = rxFifo.io.enq.fire
val isRxError = RegInit(false.B) val isRxError = RegInit(false.B)
val isAxisEnd = RegInit(false.B)
val isRxEnd = isAxisEnd & ~rxFifo.io.deq.valid
val intRxError = ~RegNext(isRxError, false.B) & isRxError val intRxError = ~RegNext(isRxError, false.B) & isRxError
val intRxValid = ~RegNext(isRxValid, false.B) & isRxValid // val intRxValid = ~RegNext(isRxValid, false.B) & isRxValid
val intRxStart = rxLen === 0.U & CDRIn.io.axis.fire
val intRxEnd = ~RegNext(isRxEnd, false.B) & isRxEnd
val rxCnt = RegInit(0.U(2.W)) val rxCnt = RegInit(0.U(2.W))
val rxData = Reg(UInt(32.W)) val rxData = Reg(UInt(32.W))
when(isTLWriteRxSoftReset ){
isAxisEnd := false.B
} .elsewhen( CDRIn.io.axis.fire & CDRIn.io.axis.bits.tlast ){
isAxisEnd := true.B
}
when( isTLWriteRxSoftReset ){ when( isTLWriteRxSoftReset ){
rxCnt := 0.U rxCnt := 0.U
@@ -189,18 +199,14 @@ class TLCDR(edge: TLEdgeIn)(implicit p: Parameters) extends TLCDRBase(edge) with
val isRead = Reg(Bool()) val isRead = Reg(Bool())
io.tla.ready := tlAReady io.tla.ready := tlAReady & txFifo.io.enq.ready & ( Mux(io.tla.bits.address(6,0) === "h1c".U & ( io.tla.bits.opcode === 4.U ), rxFifo.io.deq.valid, true.B) )
io.tld.valid := tlDValid io.tld.valid := tlDValid
io.interrupt(0) := intTxError io.interrupt(0) := intTxError
io.interrupt(1) := intTxFifoFull io.interrupt(1) := intRxError
io.interrupt(2) := intTxFinish io.interrupt(2) := intRxStart
io.interrupt(3) := intRxError
io.interrupt(4) := intRxValid
io.interrupt(3) := intRxEnd
when( io.tla.fire ) { when( io.tla.fire ) {

12
tb/sw/src/mstMain.S
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@@ -29,22 +29,14 @@ main:
li x6, 128 # 设置循环次数 li x6, 128 # 设置循环次数
li x10, 0x1234 li x10, 0x1234
1: 1:
beqz x15, 3f # 如果x10为0，则跳到3
2:
li x15, 0 # 清标志位
lw x7, 0(x5) # 读取cdr_0_tx_status的值
andi x7, x7, 0x2 # 检查第1比特（位1）
bnez x7, 2b # 如果第1比特不为0，则回到2处继续循环
3:
# 向cdr_0_tx_txFifo地址写入0x55，循环32次 # 向cdr_0_tx_txFifo地址写入0x55，循环32次
sw x10, 8(x5) # 向cdr_0_tx_txFifo写入0 sw x10, 8(x5) # 向cdr_0_tx_txFifo写入0
addi x6, x6, -1 # 递减计数器 addi x6, x6, -1 # 递减计数器
bnez x6, 1b # 如果计数器不为0，则继续循环 bnez x6, 1b # 如果计数器不为0，则继续循环
4: 2:
j 4b j 2b

4
tb/sw/src/mstStartup.S
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@@ -10,7 +10,7 @@
_prog_start: _prog_start:
li x15, 0 li x15, 0
picorv32_maskirq_insn(zero, zero) # picorv32_maskirq_insn(zero, zero)
call main call main
li gp, 1; li gp, 1;
@@ -46,7 +46,7 @@ trap_entry:
# q寄存器已经禁用， Without the q-registers, the irq return address will be stored in x3 (gp) and the IRQ bitmask in x4 (tp), # q寄存器已经禁用， Without the q-registers, the irq return address will be stored in x3 (gp) and the IRQ bitmask in x4 (tp),
addi x15, x4, 0 # addi x15, x4, 0
picorv32_retirq_insn() picorv32_retirq_insn()