From 498fa92a80fd437e1bd2016bdfb58ecb3e26a7b4 Mon Sep 17 00:00:00 2001
From: RuigeLee <wut.ruigeli@gmail.com>
Date: Wed, 30 Oct 2024 10:24:22 +0800
Subject: [PATCH] =?UTF-8?q?=E5=8D=A1=E6=80=BB=E7=BA=BF=20=E5=8F=91?=
 =?UTF-8?q?=E9=80=81=E6=AD=A3=E7=A1=AE?=
MIME-Version: 1.0
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---
 src/main/scala/backBoard/pico/TLCDR.scala | 28 ++++++++++++++---------
 tb/sw/src/mstMain.S                       | 12 ++--------
 tb/sw/src/mstStartup.S                    |  4 ++--
 3 files changed, 21 insertions(+), 23 deletions(-)

diff --git a/src/main/scala/backBoard/pico/TLCDR.scala b/src/main/scala/backBoard/pico/TLCDR.scala
index 757a7ae..a2df2c7 100644
--- a/src/main/scala/backBoard/pico/TLCDR.scala
+++ b/src/main/scala/backBoard/pico/TLCDR.scala
@@ -18,7 +18,7 @@ abstract class TLCDRBase(val edge: TLEdgeIn)(implicit p: Parameters) extends Bac
     val tla = Flipped(new DecoupledIO(new TLBundleA(edge.bundle)))
     val tld = new DecoupledIO(new TLBundleD(edge.bundle))
 
-    val interrupt = Output(Vec(5, Bool()))
+    val interrupt = Output(Vec(4, Bool()))
   }
 
   val io: TLCDRIO = IO(new TLCDRIO)  
@@ -127,14 +127,24 @@ trait TLCDRRx{ this: TLCDRBase =>
   // val isRxBusy  = RegInit(false.B)
   val isRxValid = rxFifo.io.enq.fire
   val isRxError = RegInit(false.B)
+  val isAxisEnd = RegInit(false.B)
+  val isRxEnd   = isAxisEnd & ~rxFifo.io.deq.valid
 
   val intRxError  = ~RegNext(isRxError, false.B) & isRxError
-  val intRxValid  = ~RegNext(isRxValid, false.B) & isRxValid
+  // val intRxValid  = ~RegNext(isRxValid, false.B) & isRxValid
+  val intRxStart = rxLen === 0.U & CDRIn.io.axis.fire
+  val intRxEnd   = ~RegNext(isRxEnd, false.B) & isRxEnd
 
 
   val rxCnt = RegInit(0.U(2.W))
   val rxData = Reg(UInt(32.W))
 
+  when(isTLWriteRxSoftReset ){
+    isAxisEnd := false.B
+  } .elsewhen( CDRIn.io.axis.fire & CDRIn.io.axis.bits.tlast ){
+    isAxisEnd := true.B
+  }
+
   
   when( isTLWriteRxSoftReset ){
     rxCnt := 0.U
@@ -189,18 +199,14 @@ class TLCDR(edge: TLEdgeIn)(implicit p: Parameters) extends TLCDRBase(edge) with
 
   val isRead  = Reg(Bool())
 
-  io.tla.ready := tlAReady
-  io.tld.valid := tlDValid
+  io.tla.ready := tlAReady & txFifo.io.enq.ready & ( Mux(io.tla.bits.address(6,0) === "h1c".U & ( io.tla.bits.opcode === 4.U ), rxFifo.io.deq.valid, true.B) )
+  io.tld.valid := tlDValid 
 
   io.interrupt(0) := intTxError
-  io.interrupt(1) := intTxFifoFull
-  io.interrupt(2) := intTxFinish
-
-  io.interrupt(3) := intRxError
-  io.interrupt(4) := intRxValid
-
-
+  io.interrupt(1) := intRxError
+  io.interrupt(2) := intRxStart
 
+  io.interrupt(3) := intRxEnd
 
 
   when( io.tla.fire ) {
diff --git a/tb/sw/src/mstMain.S b/tb/sw/src/mstMain.S
index 512596c..0d9ddc7 100644
--- a/tb/sw/src/mstMain.S
+++ b/tb/sw/src/mstMain.S
@@ -29,22 +29,14 @@ main:
     li   x6, 128              # 设置循环次数
     li x10, 0x1234
 1:
-	beqz x15, 3f             # 如果x10为0，则跳到3
-2:
-	li   x15, 0              # 清标志位
-    lw   x7, 0(x5)           # 读取cdr_0_tx_status的值
-    andi x7, x7, 0x2         # 检查第1比特（位1）
-    bnez x7, 2b              # 如果第1比特不为0，则回到2处继续循环
-
-3:
     # 向cdr_0_tx_txFifo地址写入0x55，循环32次
 
     sw   x10, 8(x5)          # 向cdr_0_tx_txFifo写入0
     addi x6, x6, -1         # 递减计数器
     bnez x6, 1b             # 如果计数器不为0，则继续循环
 
-4:	
-	j 4b 
+2:	
+	j 2b 
 
 
 
diff --git a/tb/sw/src/mstStartup.S b/tb/sw/src/mstStartup.S
index bd2dee0..974006b 100644
--- a/tb/sw/src/mstStartup.S
+++ b/tb/sw/src/mstStartup.S
@@ -10,7 +10,7 @@
 
 _prog_start:
 	li x15, 0
-	picorv32_maskirq_insn(zero, zero)
+	# picorv32_maskirq_insn(zero, zero)
 	call main
 
 	li gp, 1;
@@ -46,7 +46,7 @@ trap_entry:
 
 	# q寄存器已经禁用， Without the q-registers, the irq return address will be stored in x3 (gp) and the IRQ bitmask in x4 (tp),
 
-	addi x15, x4, 0
+	# addi x15, x4, 0
 
 	picorv32_retirq_insn()