卡总线 发送正确

src/main/scala/backBoard/pico/TLCDR.scala

@@ -18,7 +18,7 @@ abstract class TLCDRBase(val edge: TLEdgeIn)(implicit p: Parameters) extends Bac
     val tla = Flipped(new DecoupledIO(new TLBundleA(edge.bundle)))
     val tld = new DecoupledIO(new TLBundleD(edge.bundle))
 
-    val interrupt = Output(Vec(5, Bool()))
+    val interrupt = Output(Vec(4, Bool()))
   }
 
   val io: TLCDRIO = IO(new TLCDRIO)  
@@ -127,14 +127,24 @@ trait TLCDRRx{ this: TLCDRBase =>
   // val isRxBusy  = RegInit(false.B)
   val isRxValid = rxFifo.io.enq.fire
   val isRxError = RegInit(false.B)
+  val isAxisEnd = RegInit(false.B)
+  val isRxEnd   = isAxisEnd & ~rxFifo.io.deq.valid
 
   val intRxError  = ~RegNext(isRxError, false.B) & isRxError
-  val intRxValid  = ~RegNext(isRxValid, false.B) & isRxValid
+  // val intRxValid  = ~RegNext(isRxValid, false.B) & isRxValid
+  val intRxStart = rxLen === 0.U & CDRIn.io.axis.fire
+  val intRxEnd   = ~RegNext(isRxEnd, false.B) & isRxEnd
 
 
   val rxCnt = RegInit(0.U(2.W))
   val rxData = Reg(UInt(32.W))
 
+  when(isTLWriteRxSoftReset ){
+    isAxisEnd := false.B
+  } .elsewhen( CDRIn.io.axis.fire & CDRIn.io.axis.bits.tlast ){
+    isAxisEnd := true.B
+  }
+
   
   when( isTLWriteRxSoftReset ){
     rxCnt := 0.U
@@ -189,18 +199,14 @@ class TLCDR(edge: TLEdgeIn)(implicit p: Parameters) extends TLCDRBase(edge) with
 
   val isRead  = Reg(Bool())
 
-  io.tla.ready := tlAReady
-  io.tld.valid := tlDValid
+  io.tla.ready := tlAReady & txFifo.io.enq.ready & ( Mux(io.tla.bits.address(6,0) === "h1c".U & ( io.tla.bits.opcode === 4.U ), rxFifo.io.deq.valid, true.B) )
+  io.tld.valid := tlDValid 
 
   io.interrupt(0) := intTxError
-  io.interrupt(1) := intTxFifoFull
-  io.interrupt(2) := intTxFinish
-
-  io.interrupt(3) := intRxError
-  io.interrupt(4) := intRxValid
-
-
+  io.interrupt(1) := intRxError
+  io.interrupt(2) := intRxStart
 
+  io.interrupt(3) := intRxEnd
 
 
   when( io.tla.fire ) {