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enhance 要求先跨时钟，再进行后续表决

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Ruige Lee
2025-08-15 15:28:28 +08:00
parent 62684bd665
commit 45d2d223c1
1 changed files with 11 additions and 5 deletions
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16
src/main/scala/backBoard/ebus/CDRIn.scala
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@@ -73,18 +73,24 @@ trait CDRInMultiSample{ this: CDRInBase =>
val multiCLK = IO(Input(Vec(16, Bool()))) val multiCLK = IO(Input(Vec(16, Bool())))
val sampleReg = Wire(Vec(23, Bool())) val sampleReg = Wire(Vec(16, Bool()))
for( i <- 0 until 16 ) { for( i <- 0 until 16 ) {
sampleReg(i) := withClockAndReset(multiCLK(i).asClock, reset.asBool){ ShiftRegister( io.serDat, 2 ) } sampleReg(i) := withClockAndReset(multiCLK(i).asClock, reset.asBool){ ShiftRegister( io.serDat, 2 ) }
} }
for( i <- 16 until 23 ){
sampleReg(i) := withClockAndReset(multiCLK(i-8+1).asClock, reset.asBool){ RegNext(sampleReg(i-8+1))} val sampleReg_sync = Wire(Vec(23,Bool()))
for( i <- 0 until 7 ){
sampleReg_sync(i) := RegNext(sampleReg_sync(i+15))
}
for( i <- 7 until 23 ){
sampleReg_sync(i) := RegNext(sampleReg(i-7))
} }
val asyncSerDat = PopCount(sampleReg_sync) >= 12.U
val asyncSerDat = PopCount(sampleReg) >= 12.U
// sampleReg.count( (x: Bool) => (x === true.B) ) >= 12.U // sampleReg.count( (x: Bool) => (x === true.B) ) >= 12.U