From 45d2d223c1f620d8370013fb920b7f6d01aabd36 Mon Sep 17 00:00:00 2001 From: Ruige Lee Date: Fri, 15 Aug 2025 15:28:28 +0800 Subject: [PATCH] =?UTF-8?q?enhance=20=E8=A6=81=E6=B1=82=E5=85=88=E8=B7=A8?= =?UTF-8?q?=E6=97=B6=E9=92=9F=EF=BC=8C=E5=86=8D=E8=BF=9B=E8=A1=8C=E5=90=8E?= =?UTF-8?q?=E7=BB=AD=E8=A1=A8=E5=86=B3?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/ebus/CDRIn.scala | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/src/main/scala/backBoard/ebus/CDRIn.scala b/src/main/scala/backBoard/ebus/CDRIn.scala index 991b743..1fe1c83 100644 --- a/src/main/scala/backBoard/ebus/CDRIn.scala +++ b/src/main/scala/backBoard/ebus/CDRIn.scala @@ -73,18 +73,24 @@ trait CDRInMultiSample{ this: CDRInBase => val multiCLK = IO(Input(Vec(16, Bool()))) - val sampleReg = Wire(Vec(23, Bool())) + val sampleReg = Wire(Vec(16, Bool())) for( i <- 0 until 16 ) { sampleReg(i) := withClockAndReset(multiCLK(i).asClock, reset.asBool){ ShiftRegister( io.serDat, 2 ) } } - for( i <- 16 until 23 ){ - sampleReg(i) := withClockAndReset(multiCLK(i-8+1).asClock, reset.asBool){ RegNext(sampleReg(i-8+1))} + + val sampleReg_sync = Wire(Vec(23,Bool())) + + for( i <- 0 until 7 ){ + sampleReg_sync(i) := RegNext(sampleReg_sync(i+15)) + } + + for( i <- 7 until 23 ){ + sampleReg_sync(i) := RegNext(sampleReg(i-7)) } - - val asyncSerDat = PopCount(sampleReg) >= 12.U + val asyncSerDat = PopCount(sampleReg_sync) >= 12.U // sampleReg.count( (x: Bool) => (x === true.B) ) >= 12.U