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新需求 更新第15页

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This commit is contained in:
RuigeLee
2024-09-02 16:24:02 +08:00
parent 693621f1a0
commit 45c983acfc
9 changed files with 53 additions and 34 deletions
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9
src/main/scala/backBoard/DIn16.scala
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@@ -134,5 +134,14 @@ with BackBoardSlvIn16{
upReg(4) := digitalFilter(0)
upReg(5) := digitalFilter(1)
}
page15reg2 := 0.U
page15reg3 := 2.U
page15reg4 := 2.U
page15reg5 := 0.U
page15reg6 := 0.U
page15reg7 := 0.U
page15reg8 := 0.U
page15reg9 := 0.U
}

12
src/main/scala/backBoard/Dout16.scala
View File

@@ -56,6 +56,18 @@ with BackBoardSlvOut16{
upReg(7) := valueReg(15,8)
}
val page15reg2 := 6.U
val page15reg3 := 0.U
val page15reg4 := 4.U
val page15reg5 := 2.U
val page15reg6 := 0.U
val page15reg7 := 0.U
val page15reg8 := 0.U
val page15reg9 := 0.U
out := outPin
}

53
src/main/scala/backBoard/LocalRegisters.scala
View File

@@ -4,8 +4,6 @@ import chisel3._
import chisel3.util._
class ManualParamBundle extends Bundle{
val pl = UInt( 16.W )
val npl = UInt( 16.W )
val vendorID = UInt( 16.W )
val moduleID = UInt( 16.W )
val hwVersion = UInt( 16.W )
@@ -27,36 +25,49 @@ abstract class BackBoardSlvLocal extends BackBoardSlvBase with BackBoardSlvDown
val statusSync = RegEnable( downRegTemp(1).extract(3).asBool, false.B, isCrcPass )
val statusNone = ~ShiftRegister(io.isLast, 2)
val page15reg2 = WireDefault(0.U(8.W))
val page15reg3 = WireDefault(0.U(8.W))
val page15reg4 = WireDefault(0.U(8.W))
val page15reg5 = WireDefault(0.U(8.W))
val page15reg6 = WireDefault(0.U(8.W))
val page15reg7 = WireDefault(0.U(8.W))
val page15reg8 = WireDefault(0.U(8.W))
val page15reg9 = WireDefault(0.U(8.W))
upReg(0) := Cat( statusPR.extract(0), statusRF, statusP, 0.U(1.W), statusPage )
upReg(1) := Cat( statusNone, statusSync, statusLE, statusER, statusPR.extract(1) )
when( statusPage === 15.U ){
upReg(2) := param.pl(7,0)
upReg(3) := param.pl(15,8)
upReg(2) := page15reg2
upReg(3) := page15reg3
upReg(4) := param.npl(7,0)
upReg(5) := param.npl(15,8)
upReg(4) := page15reg4
upReg(5) := page15reg5
upReg(6) := param.vendorID(7,0)
upReg(7) := param.vendorID(15,8)
upReg(6) := page15reg6
upReg(7) := page15reg7
upReg(8) := page15reg8
upReg(9) := page15reg9
upReg(8) := param.moduleID(7,0)
upReg(9) := param.moduleID(15,8)
upReg(10) := param.hwVersion(7,0)
upReg(11) := param.hwVersion(15,8)
upReg(10) := param.vendorID(7,0)
upReg(11) := param.vendorID(15,8)
upReg(12) := param.swVersion(7,0)
upReg(13) := param.swVersion(15,8)
upReg(12) := param.moduleID(7,0)
upReg(13) := param.moduleID(15,8)
upReg(14) := param.serial(7,0)
upReg(15) := param.serial(15,8)
upReg(16) := param.serial(23,16)
upReg(17) := param.serial(31,24)
upReg(18) := param.serial(39,32)
upReg(19) := param.serial(47,40)
upReg(14) := param.hwVersion(7,0)
upReg(15) := param.hwVersion(15,8)
upReg(16) := param.swVersion(7,0)
upReg(17) := param.swVersion(15,8)
upReg(18) := param.serial(7,0)
upReg(19) := param.serial(15,8)
upReg(20) := param.serial(23,16)
upReg(21) := param.serial(31,24)
upReg(22) := param.serial(39,32)
upReg(23) := param.serial(47,40)
}