From 45c983acfc47cd09056ce53ab6dbd098821df9b4 Mon Sep 17 00:00:00 2001 From: RuigeLee Date: Mon, 2 Sep 2024 16:24:02 +0800 Subject: [PATCH] =?UTF-8?q?=E6=96=B0=E9=9C=80=E6=B1=82=20=E6=9B=B4?= =?UTF-8?q?=E6=96=B0=E7=AC=AC15=E9=A1=B5?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/DIn16.scala | 9 ++++ src/main/scala/backBoard/Dout16.scala | 12 +++++ src/main/scala/backBoard/LocalRegisters.scala | 53 +++++++++++-------- src/main/verilog/defineParam.v | 3 -- src/main/verilog/di16_top.v | 2 - src/main/verilog/do16_top.v | 2 - src/main/verilog/do16inv_top.v | 2 - src/main/verilog/qei_top.v | 2 - src/main/verilog/spi_top.v | 2 - 9 files changed, 53 insertions(+), 34 deletions(-) diff --git a/src/main/scala/backBoard/DIn16.scala b/src/main/scala/backBoard/DIn16.scala index 4f0a135..793102c 100644 --- a/src/main/scala/backBoard/DIn16.scala +++ b/src/main/scala/backBoard/DIn16.scala @@ -134,5 +134,14 @@ with BackBoardSlvIn16{ upReg(4) := digitalFilter(0) upReg(5) := digitalFilter(1) } + + page15reg2 := 0.U + page15reg3 := 2.U + page15reg4 := 2.U + page15reg5 := 0.U + page15reg6 := 0.U + page15reg7 := 0.U + page15reg8 := 0.U + page15reg9 := 0.U } diff --git a/src/main/scala/backBoard/Dout16.scala b/src/main/scala/backBoard/Dout16.scala index 351e75e..e2c59c8 100644 --- a/src/main/scala/backBoard/Dout16.scala +++ b/src/main/scala/backBoard/Dout16.scala @@ -56,6 +56,18 @@ with BackBoardSlvOut16{ upReg(7) := valueReg(15,8) } + val page15reg2 := 6.U + val page15reg3 := 0.U + val page15reg4 := 4.U + val page15reg5 := 2.U + val page15reg6 := 0.U + val page15reg7 := 0.U + val page15reg8 := 0.U + val page15reg9 := 0.U + + + + out := outPin } diff --git a/src/main/scala/backBoard/LocalRegisters.scala b/src/main/scala/backBoard/LocalRegisters.scala index bb97d4d..5cbe57a 100644 --- a/src/main/scala/backBoard/LocalRegisters.scala +++ b/src/main/scala/backBoard/LocalRegisters.scala @@ -4,8 +4,6 @@ import chisel3._ import chisel3.util._ class ManualParamBundle extends Bundle{ - val pl = UInt( 16.W ) - val npl = UInt( 16.W ) val vendorID = UInt( 16.W ) val moduleID = UInt( 16.W ) val hwVersion = UInt( 16.W ) @@ -27,36 +25,49 @@ abstract class BackBoardSlvLocal extends BackBoardSlvBase with BackBoardSlvDown val statusSync = RegEnable( downRegTemp(1).extract(3).asBool, false.B, isCrcPass ) val statusNone = ~ShiftRegister(io.isLast, 2) - + val page15reg2 = WireDefault(0.U(8.W)) + val page15reg3 = WireDefault(0.U(8.W)) + val page15reg4 = WireDefault(0.U(8.W)) + val page15reg5 = WireDefault(0.U(8.W)) + val page15reg6 = WireDefault(0.U(8.W)) + val page15reg7 = WireDefault(0.U(8.W)) + val page15reg8 = WireDefault(0.U(8.W)) + val page15reg9 = WireDefault(0.U(8.W)) upReg(0) := Cat( statusPR.extract(0), statusRF, statusP, 0.U(1.W), statusPage ) upReg(1) := Cat( statusNone, statusSync, statusLE, statusER, statusPR.extract(1) ) when( statusPage === 15.U ){ - upReg(2) := param.pl(7,0) - upReg(3) := param.pl(15,8) + upReg(2) := page15reg2 + upReg(3) := page15reg3 - upReg(4) := param.npl(7,0) - upReg(5) := param.npl(15,8) + upReg(4) := page15reg4 + upReg(5) := page15reg5 - upReg(6) := param.vendorID(7,0) - upReg(7) := param.vendorID(15,8) + upReg(6) := page15reg6 + upReg(7) := page15reg7 + upReg(8) := page15reg8 + upReg(9) := page15reg9 - upReg(8) := param.moduleID(7,0) - upReg(9) := param.moduleID(15,8) - upReg(10) := param.hwVersion(7,0) - upReg(11) := param.hwVersion(15,8) + upReg(10) := param.vendorID(7,0) + upReg(11) := param.vendorID(15,8) - upReg(12) := param.swVersion(7,0) - upReg(13) := param.swVersion(15,8) + upReg(12) := param.moduleID(7,0) + upReg(13) := param.moduleID(15,8) - upReg(14) := param.serial(7,0) - upReg(15) := param.serial(15,8) - upReg(16) := param.serial(23,16) - upReg(17) := param.serial(31,24) - upReg(18) := param.serial(39,32) - upReg(19) := param.serial(47,40) + upReg(14) := param.hwVersion(7,0) + upReg(15) := param.hwVersion(15,8) + + upReg(16) := param.swVersion(7,0) + upReg(17) := param.swVersion(15,8) + + upReg(18) := param.serial(7,0) + upReg(19) := param.serial(15,8) + upReg(20) := param.serial(23,16) + upReg(21) := param.serial(31,24) + upReg(22) := param.serial(39,32) + upReg(23) := param.serial(47,40) } diff --git a/src/main/verilog/defineParam.v b/src/main/verilog/defineParam.v index a980298..e1e4a2c 100644 --- a/src/main/verilog/defineParam.v +++ b/src/main/verilog/defineParam.v @@ -1,8 +1,5 @@ -`define PL 16'h0002 -`define NPL 16'h0004 `define VENDORID 16'h1122 `define MODULEID 16'h3344 `define HWVERSION 16'h5566 `define SWVERSION 16'h7788 -// `define BATCHID 16'h99aa `define SERIAL 48'hbbccddeeff00 \ No newline at end of file diff --git a/src/main/verilog/di16_top.v b/src/main/verilog/di16_top.v index 5a9fecd..4285f87 100644 --- a/src/main/verilog/di16_top.v +++ b/src/main/verilog/di16_top.v @@ -286,8 +286,6 @@ DIn16 i_din16( .io_isLast(isLast_temp1), .io_DCIn(DCIn), - .param_pl(`PL), - .param_npl(`NPL), .param_vendorID(`VENDORID), .param_moduleID(`MODULEID), .param_hwVersion(`HWVERSION), diff --git a/src/main/verilog/do16_top.v b/src/main/verilog/do16_top.v index 873b1f0..c5cb911 100644 --- a/src/main/verilog/do16_top.v +++ b/src/main/verilog/do16_top.v @@ -292,8 +292,6 @@ DOut16 i_dout16( .io_isLast(isLast_temp1), .io_DCIn(DCIn), - .param_pl(`PL), - .param_npl(`NPL), .param_vendorID(`VENDORID), .param_moduleID(`MODULEID), .param_hwVersion(`HWVERSION), diff --git a/src/main/verilog/do16inv_top.v b/src/main/verilog/do16inv_top.v index 14e4c62..e4acc13 100644 --- a/src/main/verilog/do16inv_top.v +++ b/src/main/verilog/do16inv_top.v @@ -292,8 +292,6 @@ DOut16 i_dout16( .io_isLast(isLast_temp1), .io_DCIn(DCIn), - .param_pl(`PL), - .param_npl(`NPL), .param_vendorID(`VENDORID), .param_moduleID(`MODULEID), .param_hwVersion(`HWVERSION), diff --git a/src/main/verilog/qei_top.v b/src/main/verilog/qei_top.v index f0e5258..b75e32d 100644 --- a/src/main/verilog/qei_top.v +++ b/src/main/verilog/qei_top.v @@ -307,8 +307,6 @@ Qei i_qei( .io_lvdsSlv_downstream_rx_cdr_err(downstream_rx_cdr_err), .io_lvdsSlv_upstream_rx_cdr_err(upstream_rx_cdr_err), - .param_pl(`PL), - .param_npl(`NPL), .param_vendorID(`VENDORID), .param_moduleID(`MODULEID), .param_hwVersion(`HWVERSION), diff --git a/src/main/verilog/spi_top.v b/src/main/verilog/spi_top.v index c0edbf5..c542787 100644 --- a/src/main/verilog/spi_top.v +++ b/src/main/verilog/spi_top.v @@ -294,8 +294,6 @@ SpiSlv i_spiSlv( .io_isLast(isLast_temp1), .io_DCIn(DCIn), - .param_pl(`PL), - .param_npl(`NPL), .param_vendorID(`VENDORID), .param_moduleID(`MODULEID), .param_hwVersion(`HWVERSION),