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switch from 4k to 2k

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This commit is contained in:
Ruige Lee (WSL)
2023-08-22 15:32:01 +08:00
parent 704996bdfb
commit 44e8999ab0
2 changed files with 14 additions and 26 deletions
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20
src/main/verilog/backBoardMstTop.v
View File

@@ -46,20 +46,14 @@ always@(posedge clk_10m) begin
end end
Gowin_rPLL u_Gowin_rPLL( Gowin_PLLO Gowin_PLLO(
.clkout(clk_400m), //pll clkout,400MHz .lock(),
.clkoutd(clk_100m), //100MHz .clkouta(clk_400m),
.clkin(clock) //clkin,50MHz .clkoutc(clk_50m),
.clkoutd(clk_100m),
.clkin(clock)
); );
Gowin_rPLL1 u_Gowin_rPLL1(
.clkout(clk_50m), //output clkout
.lock(), //output lock
.clkin(clock) //input clkin
);
TLVDS_OBUF lvds_downstream_out( TLVDS_OBUF lvds_downstream_out(
.O(lvds_down_dout_p), .O(lvds_down_dout_p),
.OB(lvds_down_dout_n), .OB(lvds_down_dout_n),
@@ -108,4 +102,4 @@ BackBoardMst i_BackBoardMst(
endmodule endmodule

20
src/main/verilog/backBoardSlvTop.v
View File

@@ -36,19 +36,13 @@ always@(posedge clk_10m) begin
end end
Gowin_rPLL u_Gowin_rPLL( Gowin_PLLO Gowin_PLLO(
.clkout(clk_400m), //pll clkout,400MHz .lock(),
.clkoutd(clk_100m), //100MHz .clkouta(clk_400m),
.clkin(clock) //clkin,50MHz .clkoutc(clk_50m),
); .clkoutd(clk_100m),
.clkin(clock)
);
Gowin_rPLL1 u_Gowin_rPLL1(
.clkout(clk_50m), //output clkout
.lock(), //output lock
.clkin(clkin) //input clkin
);
TLVDS_OBUF lvds_downstream_out( TLVDS_OBUF lvds_downstream_out(
.O(lvds_down_dout_p), .O(lvds_down_dout_p),