diff --git a/src/main/verilog/backBoardMstTop.v b/src/main/verilog/backBoardMstTop.v
index 480d19d..8a27513 100644
--- a/src/main/verilog/backBoardMstTop.v
+++ b/src/main/verilog/backBoardMstTop.v
@@ -46,20 +46,14 @@ always@(posedge clk_10m) begin
 end
 
 
-Gowin_rPLL u_Gowin_rPLL(
-  .clkout(clk_400m), //pll clkout,400MHz
-  .clkoutd(clk_100m), //100MHz
-  .clkin(clock) //clkin,50MHz
+Gowin_PLLO Gowin_PLLO(
+    .lock(),
+    .clkouta(clk_400m),
+    .clkoutc(clk_50m),
+    .clkoutd(clk_100m),
+    .clkin(clock)
 );
 
-
-Gowin_rPLL1 u_Gowin_rPLL1(
-  .clkout(clk_50m), //output clkout
-  .lock(), //output lock
-  .clkin(clock) //input clkin
-);
-
-
 TLVDS_OBUF lvds_downstream_out(
   .O(lvds_down_dout_p),
   .OB(lvds_down_dout_n),
@@ -108,4 +102,4 @@ BackBoardMst i_BackBoardMst(
 
 
 
-endmodule
\ No newline at end of file
+endmodule
diff --git a/src/main/verilog/backBoardSlvTop.v b/src/main/verilog/backBoardSlvTop.v
index 0140989..4fae421 100644
--- a/src/main/verilog/backBoardSlvTop.v
+++ b/src/main/verilog/backBoardSlvTop.v
@@ -36,19 +36,13 @@ always@(posedge clk_10m) begin
 end
 
 
-Gowin_rPLL u_Gowin_rPLL(
-  .clkout(clk_400m), //pll clkout,400MHz
-  .clkoutd(clk_100m), //100MHz
-  .clkin(clock) //clkin,50MHz
-);
-
-
-Gowin_rPLL1 u_Gowin_rPLL1(
-  .clkout(clk_50m), //output clkout
-  .lock(), //output lock
-  .clkin(clkin) //input clkin
-);
-
+Gowin_PLLO Gowin_PLLO(
+        .lock(), 
+        .clkouta(clk_400m),
+        .clkoutc(clk_50m),
+        .clkoutd(clk_100m),
+        .clkin(clock)
+    );
 
 TLVDS_OBUF lvds_downstream_out(
   .O(lvds_down_dout_p),